MC33596_10 Datasheet, PDF (42/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

Bank Access and Register Mapping
Bits RSSI[3:0] contain the result of the analog-to-digital conversion of the signal measured at the IF filter
output.
17 Bank Access and Register Mapping
Registers are physically mapped following a byte organization. The possible address space is 32 bytes. The
base address is specified in the command byte. This is then incremented internally to address each register,
up to the number of registers specified by N[1:0], also specified by this command byte. All registers can
then be scanned, whatever the type of transmission (read or write); however, writing to read-only bits or
registers has no effect. When the last implemented address is reached, the internal address counter
automatically loops back to the first mapped address ($00).
At any time, it is possible to write or read the content of any register of Bank A and Bank B. Register access
is defined as follows:
R/W
R
RR
R [A]
RR [A]
Bit can be read and written.
Bit can be read. Write has no effect on bit value.
Bit can be read. Read or write resets the value.
Bit can be read. This returns the same value as Bank A.
Bit can be read. This returns the same value as Bank A. Read or write resets the value.
Table 20. Access to Specific Bits
Bit
RESET
OLS
Bank
A
A, B
Byte
CONFIG1
CONFIG3
LDVS
A, B
CONFIG3
SOE
A, B CONFIG2
RSSIx A, B
RSSI
Access
R/W
R-R[A]
RR-RR[A}
R/W-R[A}
R-R[A}
Comment
Available in BANKA.
Bit value is the real time status of the PLL, BANKA,
and BANKB access reflect the same value.
Bit value is the latched value of the low-voltage
detector. Read or write from any bank resets value.
SOE can be modified in BANKA. Access from BANKB
reflects BANKA value.
RSSI value is directly read from RSSI converter.
Reflected value is the same whatever the active byte.
MC33596 Data Sheet, Rev. 4
42
Freescale Semiconductor