MC33596_10 Datasheet, PDF (38/70 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

Register Description
Bit Name
Reset Value
Access
Bit 7
AFFC
0
R/W
Bit 6
IFLA
0
R/W
Bit 5
Bit 4
Bit 3
Bit 2
—
RSSIE
EDD
RAGC
0
0
1
0
—
R/W
R/W
R/W
Figure 27. COMMAND Register
Bit 1
FAGC
0
R/W
Bit 0
BANKS
1
R
Addr
$03
AFFC (Average Filter Frequency Control) enables direct control of the average filter cut-off frequency.
0 = Average filter cut-off frequency is defined by DR[1:0]
1 = Average filter cut-off frequency is defined by AFF[1:0]
IFLA (IF Level Attenuation) controls the maximum gain of the IF amplifier in OOK modulation.
0 = No effect
1 = Decreases by 20 dB (typical) the maximum gain of the IF amplifier, in OOK modulation only
The reduction in gain can be observed if the IF amplifier AGC system is disabled (by setting RAGC = 1).
RSSIE (RSSI Enable) enables the RSSI function.
0 = Disabled
1 = Enabled
EDD (Envelop Detector Decay) controls the envelop detector decay.
0 = Slow decay for minimum ripple
1 = Fast decay
RAGC (Reset Automatic Gain Control) resets both receiver internal AGCs.
0 = No action
1 = Sets the gain to its maximum value
A first SPI access allows RAGC to be set; a second SPI access is required to reset it.
FAGC (Freeze Automatic Gain Control) freezes both receiver AGC levels.
0 = No action
1= Holds the gain at its current value
BANKS indicates which register bank is active. This bit, available in Bank A and Bank B, returns the same
value.
0 = Bank B
1 = Bank A
16.3 Frequency Register
Figure 28 defines the Frequency register, F.
MC33596 Data Sheet, Rev. 4
38
Freescale Semiconductor