FMS7401 Datasheet, PDF (64/80 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401/7401L
PRODUCT SPECIFICATION
12.2.4 Program Memory Erase
The external programmer may erase the entire code EEPROM memory array using two special program erase byte write commands.
This special erase option may also be used to unlock memory protected (WDIS/RDIS=1) devices without compromising design secu-
rity. The special program erase byte write command overrides the WDIS memory security bit if set. Once both special byte write
commands are issued, the volatile Initialization Register 1 is automatically cleared to unprotect the current programming mode
session and allow complete access of the device memories.⁵ The external programmer may then re-program the code EEPROM with
a new pattern or permanently disable all security features by re-programming the non-volatile Initialization Register 1. All other
memories, including the data EEPROM, are unaffected by the program erase commands.
The special program erase protocol requires the external programmer to shift two 32-bit command words addressing two
separate page addresses. The special program erase 32-bit command word is similar to a byte write command except that bit 22
must be set to 1 to enable the program erase mode. The code EEPROM memory must also be selected by setting bit 28 of the
command word. The first command word must select all even pages of the memory by setting the address bits (bits 17 to 8) to
0x000. The second command word must select all odd pages by setting the address bits to 0x010 of the command word. Any
data value (bits 7 to 0) shifted as part of the individual command word may be used to erase the pages of the code EEPROM.
After each even/odd page program erase command is executed, the even/odd pages of the code EEPROM memory is filled with
the data supplied in the command erasing their previous program code data values. If the external programmer issues only one
of the (even/odd page) erase commands, only half the pages will be erased by the data selected and the volatile Initialization
Register 1 will not be cleared. Therefore, the current programming mode session will remain protected if either the memory
protection (WDIS/RDIS) bits are set.
After the external programmer puts the FMS7401/7401L into programming mode, the LOAD pin must be set to Vcc before
serially shifting the first 32-bit program erase command word using the SHIFT_IN and CLOCK signals. By definition, bit 31
of the command word must be shifted first and then followed by all other bits. With each bit of the 32-bit write command word
shifted, the device shifts out a bit of the 32-bit response word from the previous command through the SHIFT_OUT pin. The
external programmer may sample SHIFT_OUT after TACCESS from the rising edge of CLOCK. The serial response word sent
immediately after entering programming mode may contain indeterminate data. After all 32 bits of the command word are
shifted, the external programmer must set the LOAD signal to 0V and apply two clock pulses to the CLOCK signal, as shown
in Figure 20, to complete the program cycle. Once the LOAD signal is brought low, the SHIFT_OUT pin acts as the handshak-
ing signal between the device and external programmer hardware. When executing the write command, the device sets
SHIFT_OUT low by the time the external programmer has issued the second rising edge of CLOCK informing the external
programmer that the memory write is in progress. The external programmer must wait TREADY for SHIFT_OUT to return high
before returning the LOAD signal to Vcc to initiate the second program erase command cycle. The volatile Initialization
Register 1 will only be cleared if both commands are successfully executed. All other memory accesses from this point forward
are executed normally.
1. During in-circuit programming, G5 must be either not connected or driven high.
2. The following characteristics are guaranteed by design but are not 100% tested.
3. For addition detail regarding the device power-up and reset conditions refer the Reset Circuit section of the datasheet.
4. Each page in the code EEPROM has 16 bytes and starts at address 0xC00, 0xC10, 0xC20, etc.
5. For additional details regarding the WDIS, RDIS, and initialization registers, refer to the Device Memory section of the datasheet.
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REV. 1.0.2 6/23/04