FMS7401 Datasheet, PDF (47/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401/7401L
10 8-Bit Microcontroller Core
The FMS7401/7401L’s 8-bit microcontroller core is specifically designed for low cost applications involving bit manipulation,
shifting and block encryption. It is based on a modified Harvard architecture meaning peripheral, I/O and RAM locations are
addressed separately from instruction data.
The core differs from the traditional Harvard architecture by aligning the data and instruction memory sequentially. This
allows the X-pointer (11-bits) to point to any memory location in either segment of the memory map. This modification
improves the overall code efficiency of the microcontroller core and takes advantage of the flexibility found on the von Neu-
mann architecture and stored program concept.
10.1 Core Registers
The microcontroller core has five general-purpose registers. These registers are the Accumulator (A), X-Pointer (X), Program
Counter (PC), Stack Pointer (SP) and Status Register (SR). The X, SP and SR registers are memory mapped while A and PC
are not.
Figure 17. Core Program Model
A
7
0 8-bit accumulator register
X 10
0 11-bit X pointer register
PC
9
0 10-bit program counter
SP
3 0 4-bit stack pointer
SR
R 0 0 G Z C H N 8-bit status register
NEGATIVE flag
HALF CARRY flag
CARRY flag
ZERO flag
GLOBAL INTERRUPT enable
READY flag
REV. 1.0.2 6/23/04
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