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FMS7401 Datasheet, PDF (45/80 Pages) Fairchild Semiconductor – Digital Power Controller | |||
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PRODUCT SPECIFICATION
FMS7401/7401L
9 Multi-input Wakeup Circuit
The Multi-input Wakeup (MIW) circuit may be used to wake the device from either Halt or Idle Mode1 with an external event,
generate ï¬ags for software monitoring and microcontroller hardware interrupts by any one or all I/O ports (G0âG7). The MIW
circuit is conï¬gured using the Wakeup Enable (WKEN), Wakeup Edge (WKEDG), Wakeup Pending (WKPND) and
T0CNTRL memory mapped registers.2 The WKEN, WKEDG and WKPND are 8-bit registers where each bit corresponds to
an I/O port pin (see Table 21). All four registers are initialized to 0x00 upon a system reset.
The PWMOFF output signal may also be programmed as an input of the G6 port MIW circuit. Interrupts may be triggered if
the PWMOFF/G6 input MIW circuit is enabled and conï¬gured to trigger its microcontroller hardware interrupt (EDGEI).
Bit 6 (PWMINT) of the DDELAY register, if set to 1, selects the PWMOFF signal in place of its G6 input to the MIW circuit.
Software must then enable the MIW PWMOFF/G6 circuit by setting the WKEN[6] bit. The WKEDG[6] bit must also be
cleared to select the rising edge transitions on the PWMOFF signal as its WKPND[6] bit trigger. Software may monitor the
WKPND[6] ï¬ag or enable the MIW hardware interrupt (EDGEI) to help detect when the PWMOFF signal is triggered. Refer
to the Programmable Comparator Circuit sections of the datasheet for addition details.
9.1 MIW Conï¬guration Registers
The Wakeup Enable (WKEN) register individually enables an I/O portâs edge transition to trigger a wakeup/interrupt pending
ï¬ag. If the WKEN register bit is 1, the corresponding I/O portâs MIW circuitry (deï¬ned by its bit number) is enabled; other-
wise, the port circuitry remains disabled and the pending ï¬ag may not be triggered.
The Wakeup Edge (WKEDG) register bits are used to program an enabled I/O portâs pending ï¬ag to be triggered from either a
rising-/falling-edge transition. If the WKEDG register bit is 1, a falling-edge transition of the enabled I/O port will trigger the
pending ï¬ag. If zero, a rising-edge transition of the enabled I/O port will trigger the pending ï¬ag.
The MIW circuit shares a single hardware interrupt (EDGEI) among all pending ï¬ags and is enabled by the Wakeup Interrupt
enable (WKINTEN) bit of the T0CNTRL register.2 The WKINTEN bit enables hardware interrupts for the MIW circuit if set
to 1.3
The Wakeup Pending (WKPND) register contains the pending ï¬ags corresponding to each of the I/O port pins. If a WKPND
register bit is 1, the programmed I/O port edge transition has triggered its pending ï¬ag. If zero, the ï¬ag is not pending and no
transition has occurred from the last pending reset. A pending ï¬ag may only be triggered by enabled I/O ports (if its WKEN
register bit is 1). Once a pending ï¬ag is triggered, all ï¬ags are logically-ORed together to trigger a WAKEOUT if in Halt/Idle
Mode and/or hardware interrupts (if enabled). If software is to re-enter Halt/Idle Mode, all pending ï¬ags must be cleared, oth-
erwise the command is ignored. Since all MIW pending ï¬ags share a single hardware interrupt, software must take care with
the handling of the pending ï¬ags when more than one pending ï¬ag is enabled. As long as a MIW pending ï¬ag is set, the hard-
ware interrupt will continue to execute softwareâs MIW interrupt service routine with highest priority until all pending ï¬ags are
cleared.4
Upon exiting Halt/Idle Mode or before leaving softwareâs MIW interrupt service routine, the RBIT instruction may be used to
clear a particular pending ï¬ag. The RBIT instruction takes two instruction clock cycles to complete its execution. In the ï¬rst
cycle, all eight register bits are automatically read to obtain their most current value. In the second cycle, the bit to be cleared is
given its new value and all bits are then re-written to the register. Using the RBIT instruction to clear an individual pending ï¬ag
causes no potential hazards if only one wakeup I/O port is enabled. However, if more than one I/O port is enabled software
may inadvertently clear a recently triggered pending ï¬ag if the trigger happened during the second phase of the RBIT instruc-
tion execution. To avoid this condition, the LD instruction must be used to clear a set pending ï¬ag. The MIW circuit is
designed such that software may not trigger a pending ï¬ag by writing a 1 to a WKPND register bit, it may only be cleared. The
action of writing a 1 to a WKPND register bit holds the current bit value. The action of writing a 0 to a WKPND register bit
clears the bit value. Therefore, the âLD WKPND, #0F7Hâ instruction will clear the WKPND[3] while all others bits remain the
same.
REV. 1.0.2 6/23/04
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