FMS7401 Datasheet, PDF (21/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
Table 7. ADCNTRL2 Register Bit Definitions
ADCNTRL2 Register (addr. 0xA0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
REFBY2
COMPSEL
ENAMP
ENDAS
ASPEED[1:0]
FMS7401/7401L
Bit 1
ENIS
Bit 0
GAIN
Bit
REFBY2
COMPSEL
ENAMP
ENDAS
ASPEED[1:0]
ENIS
GAIN
Description
Used to divide the reference clock for the PLL and digital filter of the Programmable Comparator circuit. Refer to the Clock
Circuit section of the datasheet for details.
(0) FRCLK2=FRCLK1
(1) FRCLK2=FRCLK1/2
(0) G4 is connected to the Programmable Comparator’s non-inverting input.
(1) G2 is connected to the Programmable Comparator’s non-inverting input.
(0) Disables the Uncommitted Amplifier (G6 and G7 are normal I/Os).
(1) Enables the Uncommitted Amplifier where G6/-AIN is the inverting input and G7/AOUT is the amplifier output. The
amplifier output (AOUT) is also the ACH5 input to the ADC’s analog mux.
(0) Enables the Standard ADC Conversion Mode where software must trigger an ADC conversion by setting the ASTART
bit of the ADCNTRL1 register.
(1) Enables the ADC Gated Auto-sampling Mode where PWM Timer 1’s ADSTROBE output to automatically triggers an
ADC conversion.
(0) ADC conversion clock speed = FADCLK
(1) ADC conversion clock speed = FADCLK/2
(2) ADC conversion clock speed = FADCLK/4
(3) ADC conversion clock speed = FADCLK/8
(0) Disable Current Source Generator (G3 is a normal I/O).
(1) Enable Current Source Generator where G3/AIN1 sources the ISRC.
(0) Disables the Autozero Amplifier (G4 is a normal I/O).
(1) Enables the Autozero Amplifier (with a gain of 16) where G4/AIN0 is its non-inverting input and SR_GND is it inverting
input.
4.2 ADC Conversion Modes
The ADC circuit may be configured to convert analog voltages with a conversion cycle time determined by the ADC clock
(FADCLK) and the ASPEED bits of the ADCNTRL2 register. Refer to the following ADC Conversion Clock Configuration
section for details. By default, the ADC circuit performs a conversion with every trigger initiated by software setting the
ASTART bit of the ADCNTRL1 register to 1. The ADC circuit may also be configured to perform a conversion automatically
(using the gated auto-sampling mode) with every active (on) edge of the PWM Timer 1 ADSTROBE output signal. Refer to the
following ADC Gated Auto-sampling Mode section for details.
Before any ADC conversion triggers are issued (by software or automatically) software must configure the voltage reference
(VAREF) and analog input channel appropriately. This is done by programming the REFSEL and ACHSEL bits of the
ADCNTRL1 register. If using the internal Autozero Amplifier, Uncommitted Amplifier, and Current Source Generator circuits
in the application, software must also configure and enable the desired circuits. Lastly, the FADCLK must be configured to
improve the ADC conversion accuracy.
When performing an ADC conversion where software triggers the conversion, the ASTART bit of the ADCNTRL1 register
remains high (1) symbolizing that a conversion is in progress. The ADC conversion is divided in two phases lasting a total of
13 conversion clock cycles. However, an autozero ADC conversion lasts a total of 20 conversion clock cycles. Refer to the fol-
lowing Autozero Amplifier section for details. In the first phase of a standard conversion, occupying the first four conversion
cycles, the ADC circuit performs a sample and hold operation to measure fast changing analog signals before converting the
input voltage. The second phase, occupying the last nine cycles, converts the analog input voltage to an 8-bit digital value and
stores it in the ADATA register for easy access by software. Once the converted value is stored in ADATA, the APND bit is trig-
gered and ASTART bit is cleared (symbolizing completion of the conversion cycle). Software cannot rely on the APND bit for
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