FMS7401 Datasheet, PDF (62/80 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401/7401L
PRODUCT SPECIFICATION
between the device and external programmer hardware. The device sets SHIFT_OUT low during a page-write command by the
time the external programmer has issued the second rising edge of CLOCK informing the programmer that the memory write
is in progress. The external programmer must wait TREADY for SHIFT_OUT to return high before returning the LOAD signal to
Vcc to initiate the next command cycle.
12.2.3 Byte Read Sequence
The external programmer can only perform memory reads a byte at a time. Before shifting each new command, the external
programmer must set the LOAD signal to Vcc. By definition, bit 31 of the command word must be shifted first followed by all
other bits. With each bit of the 32-bit read command word shifted, the device shifts out a bit of the 32-bit response word from
the previous command through the SHIFT_OUT pin. The external programmer must sample SHIFT_OUT after TACCESS from
the rising edge of CLOCK. The serial response word sent immediately after entering programming mode may contain indeter-
minate data.
After all 32 bits of the read command word are shifted, the external programmer must set the LOAD signal to 0V and apply
two clock pulses to the CLOCK signal, as shown in Figure 20, to complete the read cycle. At the rising edge of the second
clock pulse, the data read from the address provided in the read command word is latched into the lower 8-bits of its response
word. Once LOAD is returned to Vcc, the next 32-bit command word may be shifted while the response word to the previous
read command is shifted out with the data read from memory. If the last read command has been shifted, a dummy read com-
mand must be shifted to collect the last response word containing the last data byte read.
Table 33. 32-Bit Command and Response Word
Bit Number
Input Command Word
Output Response Word
Bit 31
Set to 1 to enable page mode memory access otherwise 0 for byte Same as the input command word.
mode.
Bit 30
Must be set to 0.
Same as the input command word.
Bit 29
Set to 1 to access the data memory space (data EEPROM or
initialization registers) otherwise 0.
Same as the input command word.
Bit 28
Set to 1 to access the code EEPROM otherwise 0.
Same as the input command word.
Bits 27 – 25
Must be set to 0.
Same as the input command word.
Bit 24
Set to 1 to perform a read or 0 to perform a write.
Same as the input command word.
Bit 22
Set to 1 to perform a program memory erase otherwise 0.
Same as the input command word.
Bits 23, 21 – 18
Must be set to 0.
Same as the input command word.
Bits 17 – 8
Lower 10-bits of the memory mapped address byte to read/write or Same as the input command word.
first byte of the page to write.
Bits 7 – 0
Data to be programmed if a write command or all zeros if a read
command.
Same as the previous input write command word
or the data read after an input read command
word.
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REV. 1.0.2 6/23/04