FMS7401 Datasheet, PDF (33/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401/7401L
Bit 4 of the PSCALE register is the frequency selection (FSEL) bit for the Timer 1 circuit. FSEL is used to select between the
slow or high frequency options, ultimately selecting the FT1CLK to be sourced either by the FICLK or FPWMCLK (see Table 13).
If FSEL=0, the slow frequency option is selected and the FICLK will then source the FT1CLK with either a 1/8MHz frequency
determined by the FMODE bit, as discussed later in the section. If FSEL=1, the high frequency option is selected and the
FPWMCLK will then source the FT1CLK at a frequency selected by the FS[1:0] bits. The FSEL bit may not be set if the PLL is not
enabled (PLLEN=0) or changed while the Timer 1 circuit is in run mode. Any attempts to write to FSEL under this condition
will be ignored and its value will remain unchanged.
Bit 3 (FMODE) of the PSCALE register is the frequency selection bit for the main instruction clock (FICLK). FMODE is used
to select between the slow or high frequency options, ultimately selecting the FICLK to be sourced either by the internal oscilla-
tor (or the external digital clock) operating at FOSC2 or the PLL’s F(FS=0) output signal.³ If FMODE=0, the slow frequency
option is selected and the internal oscillator will then source the FICLK at a FOSC/2 frequency. If FMODE=1, the high frequency
option is selected and the F(FS=0) will then source the FICLK with PLL’s divide-by-8 output frequency. With the FMODE bit
enabled, it is possible to execute instructions at a speed approximately eight times faster than the standard. The FMODE bit
may not be set if the PLL is not enabled (PLLEN=0). Any attempts to write to FMODE while PLLEN=0 will force FMODE=0
ignoring any set instructions. Once the PLL has been enabled, software may change FICLK’s clock source on-the-fly during
normal instruction execution in order to speed-up a particular action.
Bits 2-0 of the PSCALE register are the three prescaler (PS[2:0]) bits used to divide the FT1CLK to obtain a wider frequency
range on the PWM output signals (see Table 14). The PS bits are used by the Timer 1 circuit to increment the 12-bit TMR1 at a
frequency equal to FT1CLK divided-by 1 through 8. The PS bits (like FS) may be changed by software at any time; however, if
the Timer 1 circuit is in run mode, the PS value will not change the prescale division factor until after the TMR1 counter over-
flows ending the current PWM cycle. The last PS value at the TMR1 counter overflow will dictate the prescale divide factor of
the FT1CLK for the next PWM cycle. When reading PS, the value reported will be the last value written by software and may not
necessarily reflect the divide factor for the current PWM cycle.
Table 12. Prescale (PSCALE) Register Bit Definitions
PSCALE Register (addr. 0xA4)
Bit 7
PLLEN
Bit 6
Bit 5
FS[1:0]
Bit 4
FSEL
Bit 3
FMODE
Bit 2
Bit 1
PS[2:0]
Bit 0
Bit
PLLEN
FS[1:0]
FSEL
FMODE
PS[2:0]
Description
(0) Disables the PLL circuit.
(1) Enables the PLL circuit.
PLL Divide Factor Selection Bits. Refer to Table 13 for details.
(0) Selects FICLK as Timer 1’s clock (FT1CLK) source.
(1) Selects FPWMCLK PLL output as Timer 1’s clock (FT1CLK) source.
(0) Selects FCLK divided-by-2 output as the main system instruction clock (FICLK) source.
(1) Selects F(FS=0) PLL output as the main system instruction clock (FICLK) source.
Timer 1 Prescale Selection Bits. Refer to Table 13 for details.
Table 13. PLL Divide Factor Selection Bits and the FT1CLK Resolution (FOSC=2 MHz)
FT1CLK
(FSEL=0)
Max PWM Freq.
(8-bit resolution)
FS[1:0]
FPWMCLK
FMODE=0 FMODE=1
FT1CLK
(FSEL=1)
FSEL=0
FMODE=0
FSEL=1
00
8 MHz
1 MHz
8 MHz
8 MHz
3.906 kHz
31.25 kHz
01
16 MHz
1 MHz
8 MHz
16 MHz
3.906 kHz
62.5 kHz
10
32 MHz
1 MHz
8 MHz
32 MHz
3.906 kHz
125 kHz
11
64 MHz
1 MHz
8 MHz
64 MHz
3.906 kHz
250 kHz
Max PWM Freq.
(12-bit resolution)
FSEL=0
FMODE=0
FSEL=1
244.14 Hz
1.95 kHz
244.14 Hz
3.9 kHz
244.14 Hz
7.8 kHz
244.14 Hz 15.625 kHz
REV. 1.0.2 6/23/04
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