FMS7401 Datasheet, PDF (53/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
Table 25. Instruction Cycles and Bytes
Mnemonic
ADC
ADC
ADC
ADC
ADD
ADD
ADD
ADD
AND
AND
AND
AND
CLR
CLR
CLR
DEC
DEC
DEC
IFBIT
IFBIT
IFBIT
IFC
IFEQ
IFEQ
IFEQ
IFEQ
IFEQ
IFEQ
IFGT
IFGT
IFGT
IFGT
IFGT
IFLT
IFNBIT
IFNBIT
IFNBIT
IFNC
IFNE
IFNE
IFNE
IFNE
IFNE
IFNE
INC
INC
Operand
A, [X]
A, [#,X]
A, M
A, #
A, [X]
A, [#,X]
A, M
A, #
A, [X]
A, [#,X]
A, M
A, #
X
A
M
X
A
M
#, A
#, M
#, [X]
A, [#, X]
A, [X]
A, #
A, M
M, #
X, #
A, [#, X]
A, [X]
A, #
A, M
X, #
X, #
#, A
#, M
#, [X]
A, [#, X]
A, [X]
A, #
A, M
X, #
M, #
A
M
Bytes
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
1
1
2
1
2
1
1
2
1
2
2
3
3
2
1
2
2
3
3
1
2
1
1
2
1
2
2
3
3
1
2
Cycles
1
3
2
2
1
3
2
2
1
3
2
2
1
1
1
1
1
2
1
2
1
1
3
1
2
2
3
3
3
1
2
2
3
3
1
2
1
1
3
1
2
2
3
3
1
2
Flags
affected
C,H,Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
Z,N
Z,N
Z,N
Z,N
Z,N
Z,N
Z,N
Z
C,H,Z,N
C,H,Z,N
Z
Z,N
Z,N
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,N
Z,N
FMS7401/7401L
Mnemonic
INC
INTR
INVC
JMP
JMP
JP
JSR
JSR
LD
LD
LD
LD
LD
LD
LD
LDC
NOP
OR
OR
OR
OR
RBIT
RBIT
RC
RET
RETI
RLC
RLC
RRC
RRC
SBIT
SBIT
SC
ST
ST
ST
STC
SUBC
SUBC
SUBC
SUBC
XOR
XOR
XOR
XOR
Operand
X
M
[#, X]
M
[#, X]
A, #
A, [#,X]
A, [X]
A, M
M, #
M, M
X, #
#, M
A, [X]
A, [#,X]
A, M
A, #
#, [X]
#, M
A
M
A
M
#, [X]
#, M
A, [#,X]
A, [X]
A, M
#, M
A, [X]
A, [#,X]
A, M
A, #
A, [X]
A, [#,X]
A, M
A, #
Bytes
1
1
1
3
2
1
3
2
2
2
1
2
3
3
3
2
1
1
2
2
2
1
2
1
1
1
1
2
1
2
1
2
1
2
1
2
2
1
2
2
2
1
2
2
2
Cycles
1
5
1
4
3
1
5
5
2
3
1
2
3
3
3
2
1
1
3
2
2
2
2
1
5
5
1
2
1
2
2
2
1
3
1
2
2
1
3
2
2
1
3
2
2
Flags
affected
Z
None
C
None
None
None
None
None
None
None
None
None
None
None
None
C
None
Z, N
Z,N
Z,N
Z,N
Z,N
Z,N
C,H
None
None
C,Z,N
C,Z,N
C,Z,N
C,Z,N
Z,N
Z,N
C,H
None
None
None
Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
Z,N
Z,N
Z,N
REV. 1.0.2 6/23/04
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