FMS7401 Datasheet, PDF (44/80 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401/7401L
PRODUCT SPECIFICATION
details of the port configuration options. The port configuration and data registers can both be read from or written to. Reading
PORTGP returns the value of the port pins regardless of how the pins are configured. Since this device supports MIW, all input
ports have Schmitt triggers.
Upon power-up, the PORTGC and PORTGD registers are initialized to 0x00. However, the G0/T1HS1 and G5/T1HS2 pins
may be defaulted to the different I/O configurations defined by the default I/O configuration bits of the Initialization Register 4.
Refer to Table 29 in the Device Memory section of the datasheet for details.
Table 20. I/O Register Bit Assignments
PORTGC, PORTGD, PORTGD Registers (addr. 0xB3, 0xB2, 0xB4)
Bit 7
G7²
Bit 6
G6²
Bit 5
G5³
Bit 4
G4
Bit 3
G3
Bit 2
G2
Bit 1
G1
Bit 0
G0³
Table 21. I/O Configuration Options
PORTGC Bit
0
0
1
1
PORTGD Bit
0
1
0
1
Port Pin Configuration
High-impedance input (tri-state input)
Input with pull-up (weak one input)
Push-pull zero output
Push-pull one output
1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Available only on the 14-pin package option.
3. The G0/T1HS1 and G5/T1HS2 pins on the FMS7401 have special high voltage outputs. Refer to Figure 15 for details.
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REV. 1.0.2 6/23/04