FMS7401 Datasheet, PDF (17/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
Vcc
Figure 6. ADC Block Diagram⁴
FMS7401/7401L
G3/AIN1
G2/AIN2
G1/AIN3
AGND
SR_GND
G4/AIN0
ACH5
ACHSEL[3:0]
ENIS
Sel
ACH2
ACH3
ACH4
ACH1
ACH5 ^Y
+V_REF
AGND
+V_REF
Vcc/3
Autozero
Amplifier
_
x16
+
GAIN
2R
R
R
R
COMPSEL
Vcc
+
-
G7/AIN4/A_OUT
G6/-A_IN
_
+V_REF
+
VLOOP
0.23R
R
ADSTROBE
S/H
SAR
LOGIC
8
Analog Voltage
Generator
8
+V_AREF
F_RCLK2
DELTIME
4
Programmable
Delay
PWMOFF
Voltage Level
Generator
6
COMPLEV
+V_REF
+V_REF
Vcc
A
Y ^+VAREF
B _Sel
REFSEL
B
Y
A Sel
ACH5
ENAMP
4.1.1 ADCNTRL1 Register
The ADCNTRL1 is an 8-bit memory map register used to configure and control the ADC circuits. Software has both read and write
access to all bits of the register.
Bit 7 of the ADCNTRL1 register is the ADC pending (APND) flag and is triggered after the 8-bit converted digital value is latched to
the ADATA register towards the end of the ADC conversion cycle. The APND bit may be used by software to monitor when to access
ADATA or to issue microcontroller hardware interrupts (if enabled). In order for software to monitor APND, it must be cleared before
the next converted value is latched in ADATA where the APND flag is set to 1.
REV. 1.0.2 6/23/04
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