FMS7401 Datasheet, PDF (22/80 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401/7401L
PRODUCT SPECIFICATION
this information because the APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion
completion delay may occur when the FICLK clock is slower than an ADC conversion clock cycle.
4.2.1 Analog Input Voltage and its 8-bit Digital Result
The relationship between the 8-bit digital value stored in the ADATA register and the analog input voltage is as follows:
V_ADC = ^V--_V---^A-_A--^C--_R--^H--_E--⁽-_F-^x--⁾ × 255
• VADC is the 8-bit digital result of an ADC conversion.
• VACH(x) is the analog voltage applied to the selected input channel.
4.2.2 ADC Gated Auto-sampling Mode
The ADC circuit may be configured in Gated Auto-sampling Mode by setting the ENDAS bit of the ADCNTRL2 register.
When in Auto-sampling Mode, all ADC conversions are automatically triggered by the active (on) edge transition of the PWM
Timer 1’s ADSTROBE output signal.² If the period of the PWM ADSTROBE signal is less than the total ADC conversion
time, any triggers issued while a conversion is in progress (ASTART=1) are ignored. Once the trigger is detected, the ASTART
bit of the ADCNTRL1 register is set symbolizing that a conversion is in progress. The initial conversion phase, the sample and
hold or autozero (if GAIN=1), begins after a 1µS cycle delay.⁷ Once all eight digital bits are determined and stored in the
ADATA register, the APND flag is set to trigger a hardware interrupt (if enabled) flagging software that the ADATA register has
been updated with the ADC conversion results. Once all phases of the ADC conversion cycle completes, the ASTART bit is
then automatically cleared by the ADC circuit. Since software cannot change the ADC circuit configuration while an ADC con-
version is in progress, the ASTART bit must be monitored to determine when the conversion cycle completes. Software cannot
rely on the APND bit for this information because the APND bit may be triggered before the ASTART is automatically cleared.
The ADC conversion completion delay may occur when the FICLK clock is slower than an ADC conversion clock cycle.
4.2.3 ADC Conversion Clock Configuration
The ADC conversion clock (FADCLK) is sourced either by the device’s main system instruction clock (FICLK) or the PWM Timer
1’s clock (FT1CLK) depending on the ADC circuit’s operating mode. If the standard ADC conversion mode is selected, the ADC
circuit is automatically configured to source the FADCLK clock by the FICLK clock. If the ADC Conversion Auto-sampling Mode
is selected, the ADC circuit is automatically configured to source the FADCLK clock by the FT1CLK clock to synchronize the ADC
conversions with the active (on) edge of the PWM Timer 1 ADSTROBE output signal.²
When in standard ADC conversion mode, the ASPEED[1:0] bits of the ADCNTRL2 register may be used to slow the total con-
version time improving the ADC conversion accuracy. However, if the FICLK clock is sourced by the PLL’s F(FS=0) output (when
FMODE=1) the FADCLK will clock eight times faster than the proper conversion rate (1µS cycle time). The FADCLK clock must
then be divided by setting the ASPEED[1:0]=3 divide factor to yield a FADCLK/8 conversion clock cycle. Otherwise, software
may temporarily clear FMODE returning the conversion cycle to its proper frequency and free the ASPEED bits to be used to
improve the conversion accuracy. In addition, if the internal oscillator is trimmed to its upper FOSC frequency and it is sourcing
the FICLK clock, the ASPEED[1:0]=1 divided factor must be selected to yield a FADCLK/2 conversion clock cycle.⁸ A greater
divide factor may still be selected by setting the ASPEED[1:0]>1.
When in ADC Conversion Auto-sampling Mode, the ADC circuit automatically configures the FADCLK clock to be sourced by
the FT1CLK clock so that the ADC conversions may be synchronized with the active (on) edge of the ADSTROBE signal. How-
ever, the FT1CLK clock is first sent into a special divide circuit which evaluates its configuration to determine the divide factor
needed to yield the proper FADCLK conversion rate (1µS cycle time). The FMODE, FSEL, and FS bits of the PSCALE register
are evaluated so that the divide circuit applies the appropriate divide factor to the FT1CLK clock (the PS bits do not apply). The
ASPEED[1:0] bits of the ADCNTRL2 register may be used to slow the total conversion time improving the ADC conversion
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REV. 1.0.2 6/23/04