FMS7401 Datasheet, PDF (31/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401/7401L
Table 11. Digital Delay (DDELAY) Register Bit Definitions
DDELAY Register (addr. 0xA2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
COMPEN
PWMINT
EPWM
OFFMODE
Bit 2
Bit 1
DD[3:0]
Bit 0
Bit
COMPEN
PWMINT
EPWM
OFFMODE
DD[3:0]
Description
(0) Disable the Programmable Comparator circuit.
(1) Enable the Programmable Comparator circuit.
(0) The input of the G6 MIW circuit network is the G6/-AIN device pin.
(1) The input of the G6 MIW circuit network is the PWMOFF output signal (not the G6/-AIN device pin).
(0) Enables the Digital Delay Filter circuit. The PWMOFF output is triggered by COUT after the programmed delay (TDDELAY).
(1) Disables the Digital Delay Filter circuit and the PWMOFF output signal.
(0) PWM outputs switched off and Timer 1 stops after a comparator detection with delay.
(1) PWM outputs switched off for the current PWM cycle only.
Digital delay after COUT triggers high, TDDELAY = DD • (1/FRCLK2)
Figure 10. Digital Delay Timing
Comparator
Output
Digital
Delay
Start
PWMOFF
T_DDELAY
Sample
T1HS1
T1HS2
1. Refer to the ADC Circuit section of the datasheet for additional details.
2. Refer to the I/O Ports section of the datasheet for details.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit
Microcontroller Core section of the datasheet for details.
4. Refer to the Clock Circuit section of the datasheet for details regarding the FRCLK2 clock.
REV. 1.0.2 6/23/04
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