FMS7401 Datasheet, PDF (19/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401/7401L
Table 5. ADCNTRL1 Register Bit Definitions
ADCNTRL1 Register (addr. 0x9F)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
APND
AINTEN
ASTART
REFSEL
Bit 2
Bit 1
ACHSEL[3:0]
Bit 0
Bit
APND
AINTEN
ASTART
REFSEL
ACHSEL[3:0]
Description
(0) ADC’s pending flag is cleared.
(1) ADC’s pending flag is triggered.
(0) Disables ADC hardware interrupts.
(1) Enables ADC hardware interrupts.
(0) ADC conversion is not in progress.
(1) Start an ADC conversion / ADC conversion in progress.
(0) ADC Reference (VAREF) = Internal VREF
(1) ADC Reference (VAREF) = Vcc
Analog Input Channel Selection Bits. Refer to Table 6 for details.
Table 6. Analog Input Channel Selection (ACHSEL[3:0]) Bit Definitions
ACHSEL[3]
0
0
0
0
1
1
1
1
ACHSEL[2]
0
0
0
0
0
0
0
1
ACHSEL[1]
0
0
1
1
0
0
1
0
ACHSEL[0]
0
1
0
1
0
1
0
0
Analog Channel
ACH1
ACH2
ACH3
ACH4
ACH5
AGND
+VREF
Vcc/3
I/O Equiv.
G4/AIN0
G3/AIN1
G2/AIN2
G1/AIN3
G7/AIN4/AOUT
-
-
-
4.1.2 ADCNTRL2 Register
The ADCNTRL2 is an 8-bit memory map register used to configure the analog circuits. Six of the eight register bits are used to
configure circuits directly related to the ADC circuit while the others are not related.
Bit 7 (REFBY2) of the ADCNTRL2 register is the reference clock (FRCLK1) divide-by-2 enable bit. The REFBY2 bit config-
ures the reference clock of the PLL and Programmable Comparator circuit to be sourced either by FRCLK1 or FRCLK1/2 clock.
Refer to the Clock Circuit section of the datasheet for additional details.
Bit 6 (COMPSEL) of the ADCNTRL2 register is the Programmable Comparator’s non-inverting input selection bit. If
COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the
non-inverting input of the Programmable Comparator is the G2/AIN2 device pin. Before enabling the Programmable
Comparator circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry.⁹
Refer to the Programmable Comparator Circuit section of the datasheet for addition details.
Bit 5 of the ADCNTRL2 register is the Uncommitted Amplifier Enable (ENAMP) bit. If ENAMP=0, the Uncommitted Ampli-
fier circuit is disabled and its pin connections (G6/-AIN and G7/AOUT) may be used as normal I/O ports. The G7/AIN4 pin may
still be used as a standard ADC conversion input through the analog ACH5 channel. If ENAMP=1, the Uncommitted Amplifier
circuit is enabled and its pin connections must be configured as tri-state inputs where G6/-AIN is the inverting input and G7/
AOUT is the amplifier output.⁹ If the ADC circuit is performing a conversion on the analog ACH5 input when driven by the
Uncommitted Amplifier, software must avoid clearing the ENAMP bit. Refer to the following Uncommitted Amplifier section
for additional details.
Bit 4 (ENDAS) of the ADCNTRL2 register enables the ADC conversion’s gated auto-sampling operating mode. If ENDAS=1,
the ADC circuit configures the FADCLK clock for synchronization with the PWM Timer 1’s ADSTROBE output signal. The
ADC circuit will then accept triggers by the active (on) edge transition of the ADSTROBE signal. All other ADC configuration
REV. 1.0.2 6/23/04
19