FMS7401 Datasheet, PDF (15/80 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401/7401L
1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit.
2. If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must
be set after the appropriate TPLL_LOCK wait time.
3. Prior to entering Idle Mode, software must clear both FMODE and FSEL (the timer must be disabled in order to clear
either bit) keeping the PLLEN bit 1.
4. Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit.
5. Software may then instruct the device to enter Idle Mode.
6. If all disabled circuits must be re-enabled after exiting from Idle Mode, repeat all initial steps enabling all circuits in the
appropriate order as well as waiting TPLL_LOCK.
1. Contact your local Fairchild Sales Representative for FMS7401 availability.
2. The MIW and Timer 0 Circuits are described later in the datasheet.
3. Refer to the Electrical Characteristics section of the datasheet for details.
4. Refer to the Clock Circuit’s PLL section of the datasheet for details.
5. The FSEL bit in the PSCALE register must be set.
REV. 1.0.2 6/23/04
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