CS4231A Datasheet, PDF (7/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
TIMING PARAMETERS (T_A = 25 °C; VA1, VA2, VD1-VD4 = +5V, outputs loaded with 30 pF;
Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4)
Parameter
Symbol
Min
Max
Units
WR or RD strobe width
tSTW
90
ns
Data valid to WR rising edge
(write cycle) tWDSU
22
ns
RD falling edge to data valid
(read cycle) tRDDV
60
ns
CS setup to WR of RD falling edge
tCSSU
10
ns
CS hold from WR or RD rising edge
t_CSHD
0
ns
ADDR <> setup to RD or WR falling edge
t_ADSU
22
ns
ADDR <> hold from WR or RD rising edge
tADHD
10
ns
DAK inactive to WR or RD falling edge (DMA cycle
tSUDK1
60
ns
completion immediately followed by a non-DMA cycle)
DAK active from WR or RD rising edge (non-DMA cycle
t_SUDK2
0
ns
completion immediately followed by DMA cycle)
DAK setup to RD falling edge (DMA cycles)
tDKSUa
25
ns
DAK setup to WR falling edge
tDKSUb
25
ns
Data hold from WR rising edge
tDHD2
15
ns
DRQ hold from WR or RD falling edge
(assumes no more DMA cycles needed)
t_DRHD
0
25
ns
Time between rising edge of WR or RD to next falling edge tBWND
80
ns
of WR or RD
Data hold from RD rising edge
t_DHD1
0
20
ns
DAK hold from WR rising edge
DAK hold from RD rising edge
t_DKHDa
25
ns
tDKHDb
25
ns
DBEN or DBDIR active from WR or RD falling edge
tDBDL
40
ns
PDWN pulse width low
tPDWN
200
ns
Crystals, XTAL1I, XTAL2I frequency
(Notes 1,7,8)
25.6
MHz
XTAL1I, XTAL2I high time
(Notes 1,8)
18
ns
XTAL1I, XTAL2I low time
(Notes 1,8)
18
ns
Sample frequency
(Note 1) Fs
5.5
50
kHz
Serial Port Timing
SCLK frequency
(Note 9) tSCLKW
Fsx64
Hz
SCLK rising to SDOUT valid
tPD1
30
ns
SCLK rising to FSYNC transition
t_PD2
-20
20
ns
SDIN valid to SCLK falling
t_S1
30
ns
SDIN hold after SCLK falling
tH1
30
ns
Notes:
7. When only one crystal is used, it must be XTAL1. When using two crystals, the high frequency
crystal should be on XTAL1 which is designed for higher loop gains.
8. Sample frequency specifications must not be exceeded.
9. When SF1, 0 = 10, 32-bit mode, SCLK is active for the first 32 bit periods of the frame, and remains
low during the last 32 bit periods of the frame.
DS139PP2
7