CS4231A Datasheet, PDF (52/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
XTAL2I - Crystal #2 Input, Pin 21 (L), Pin 16 (Q).
If a second crystal is used, it should be placed between this pin and XTAL2O. The standard
crystal frequency is 16.9344 MHz although other frequencies can be used. The crystal should
be designed for fundamental mode, parallel resonance operation.
XTAL2O - Crystal #2 Output, Pin 22 (L), Pin 17 (Q).
This pin is used for a crystal placed between this pin and XTAL2I.
PDWN - Power Down, Input, Pin 23 (L), Pin 18 (Q).
Places CS4231A in lowest power consumption mode. All sections of the CS4231A, except the
digital bus interface which reads 80h, are shut down and consuming minimal power. The
CS4231A is in power down mode when this pin is logic low.
XCTL0, XCTL1 - External Control, Output, Pin 56, 58 (L), Pin 71, 73 (Q).
These signals are controlled by the register bits XCTL0 and XCTL1 in register I10. They can
be used to control external logic via TTL levels.
VREF - Voltage Reference, Output, Pin 32 (L), Pin 35 (Q).
All analog inputs and outputs are centered around VREF which is nominally 2.1 Volts. This pin
may be used to level shift external circuitry, although any AC loads should be buffered. High
internal-gain microphone inputs S/N ratio can be slightly improved by placing a 10µF capacitor
on VREF.
VREFI - Voltage Reference Internal, Input, Pin 33 (L), Pin 38 (Q).
Voltage reference used internal to the CS4231A must have a 0.1 µF + 10 µF capacitor with
short fat traces to attach to this pin. No other connections should be made to this pin.
LFILT - Left Channel Antialias Filter Input, Pin 31 (L), Pin 33 (Q).
A 1000 pF NPO capacitor must be attached between this pin and analog ground.
RFILT - Right Channel Antialias Filter Input, Pin 26 (L), Pin 25 (Q).
A 1000 pF NPO capacitor must be attached between this pin and analog ground.
TEST - Test, Pin 55 (L), Pin 70 (Q).
This pin must be tied to ground for proper operation.
Power Supplies
VA1, VA2 - Analog Supply Voltage, Pin 35, 36 (L), Pin 41, 42 (Q).
Supply to the analog section of the codec.
AGND1, AGND2 - Analog Ground, Pin 34, 37 (L), Pin 40, 43 (Q).
Ground reference to the analog section of the codec. Internally, these pins are connected to the
substrate as are DGND3/4/7/8; therefore optimum layout is achieved with the AGND pins on
the same ground plane as DGND3/4/7/8 (see Figure 17). However, other ground arrangements
should yield adequate results.
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DS139PP2