CS4231A Datasheet, PDF (40/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
Right Line Input Control (I19)
D7 D6 D5 D4 D3 D2 D1 D0
RLM res res RLG4 RLG3 RLG2 RLG1 RLG0
RESERVED (I22)
D7 D6 D5 D4 D3 D2 D1 D0
res res res res res res res res
RLG4-RLG0
Right Line, RLINE, Mix Gain. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 5.
RLM
Right Line Mute. When set to 1, the
Right Line input, RLINE, to the
mixer, is muted.
This register’s initial state after reset is: 1xx01000.
Timer Lower Base (I20)
D7 D6 D5 D4 D3 D2 D1 D0
TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
TL7-TL0
Lower Timer Bits: This is the low order
byte of the 16-bit timer base register.
Writes to this register cause both
timer base registers to be loaded
into the internal timer; therefore, the
upper timer register should be
loaded before the lower. Once the
count reaches zero, an interrupt is
generated, if enabled, and the timer
is automatically reloaded with these
base registers.
This register’s initial state after reset is: xxxxxxxx
Alternate Feature Enable III (I23)
D7 D6 D5 D4 D3 D2
res res res res res res
D1 D0
res ACF
ACF
ADPCM Capture Freeze. When set,
the capture ADPCM accumulator
and step size are frozen. This bit
must be clear for adaptation to con-
tinue. Used when pausing a capture
stream.
This register’s initial state after reset is: xxxxxxx0
This register’s initial state after reset is: 00000000.
Timer Upper Base (I21)
D7 D6 D5 D4 D3 D2 D1 D0
TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0
TU7-TU0
Upper Timer Bits: This is the high
order byte of the 16-bit timer. The
time base is determined by the clock
source selected from C2SL in I8:
C2SL = 0 - divide XTAL1 by 245
(24.576 MHz - 9.969 µs)
C2SL = 1 - divide XTAL2 by 168
(16.9344 MHz - 9.92 µs)
This register’s initial state after reset is: 00000000
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DS139PP2