CS4231A Datasheet, PDF (41/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
Alternate Feature Status (I24)
D7 D6 D5 D4 D3 D2 D1 D0
res TI CI PI CU CO PO PU
PU
Playback Underrun: This bit, when set,
indicates that the DAC has run out
of data and a sample has been
missed.
PO
Playback Overrun: This bit, when set,
indicates that the host attempted to
write data into a full FIFO and the
data was discarded.
CO
Capture Overrun: This bit, when set,
indicates that the ADC had a sample
to load into the FIFO but the FIFO
was full. In this case the bit is set
and the new sample is discarded.
CU
Capture Underrun: This bit indicates
that the host has read more data out
of the FIFO than it contained. In this
condition, the bit is set and the last
valid byte is read by the host.
PI
Playback Interrupt: This bit indicates
that an interrupt is pending from the
playback DMA count registers.
When SDC = 1, this bit responds for
both capture and playback.
CI
Capture Interrupt: This bit indicates
that an interrupt is pending from the
record DMA count registers. When
SDC=1, this bit is non-functional.
TI
Timer Interrupt: This bit indicates that
an interrupt is pending from the
timer count registers
The PI, CI, and TI bits are reset by writing a "0" to
the particular interrupt bit or by writing any value to
the Status register (R2).
This register’s initial state after reset is: x0000000
Version / ID (I25)
D7 D6 D5 D4
V2 V1 V0 res
D3 D2 D1 D0
res CID2 CID1 CID0
V2-V0
Version number. As enhancements are
made to the CS4231A, the version
number is changed so software can
distinguish between the different ver-
sions.
100 - All CS4231 revisions.
See Appendix A.
101 - CS4231A. This Data Sheet.
CID2-CID0
Chip Identification. Distinguishes
between this chip and future chips
that support this register set.
000 - CS4231 or CS4231A
This register’s initial state after reset is: 101xx000
Mono Input & Output Control (I26)
D7 D6 D5 D4 D3 D2 D1 D0
MIM MOM MBY res MIA3 MIA2 MIA1 MIA0
MIA3-MIA0
MBY
MOM
Mono Input Attenuation. When MIM
is 0, these bits set the level of MIN
summed into the mixer. MIA0 is the
least significant bit and represents
3 dB attenuation, with 0000 = 0 dB.
See Table 7.
Mono Bypass. MBY connects MIN
directly to MOUT with an attenuation
of 9 dB. When MBY = 1, MIM
should be 1.
0 - MIM not connected directly to
MOUT. Use MIM and MIA bits.
1 - MIN connected to MOUT directly.
Mono Output Mute. The MOM bit will
mute the mono mix output, MOUT.
This mute is independent of the line
output mute.
0 - no mute
1 - mute
DS139PP2
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