CS4231A Datasheet, PDF (25/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
using only 8-bits per sample. This is accom-
plished using a non-linear companding transfer
function which assigns more digitalization codes
to lower amplitude analog signals with the sacri-
fice of precision on higher amplitude signals.
The µ-Law and A-Law formats of the CS4231A
conform to the CCITT G.711 specifications. Fig-
ure 11 illustrates the transfer function for both A-
and µ-Law. Please refer to the standards men-
tioned above for an exact definition.
ADPCM Compression/Decompression
In MODE 2, the CS4231A also contains Adap-
tive Differential Pulse Code Modulation
(ADPCM) for improved performance and com-
pression ratios over µ-Law or A-Law. The
ADPCM format is compliant with the IMA
standard and provides a 4-to-1 compression ratio
(i.e. 4 bits are saved for each 16-bit sample cap-
tured). For more detailed information on the
IMA ADPCM format contact the IMA at (410)
626-1380. Figures 16 and 17 illustrate the
ADPCM data flow.
The ADPCM format is unique with respect to
the FIFO depth and the DMA Base register
value. The ADPCM format fills the FIFOs com-
pletely (64 bytes); therefore, the FIFOs hold 64
stereo samples and 128 mono samples. When
samples are transferred using DMA, the DMA
request stays active for four bytes, similar to the
16-bit stereo mode. The Status register indicates
which of the four bytes is being transferred in
PIO mode.
When CEN is 0 (capture disabled), the ADPCM
block’s accumulator and step size are cleared.
When CEN is enabled, the ADPCM block will
start converting. The "overrun" condition should
never occur, otherwise the data may not be con-
structed properly upon playback. If pausing the
capture sequence is desired, the ADPCM Cap-
ture Freeze bit (ACF, I23) should be set. When
set, the ADPCM algorithm will continue to oper-
ate until a complete word (4 bytes) is written to
the FIFO. Then the ADPCM’s block accumulator
and step size will be frozen. The user is required
to read the FIFO until empty, at which time the
requests will stop. When ACF is cleared, the
ADPCM adaptation will continue.
When PEN is 0 (playback disabled), the
ADPCM block’s accumulator and step size are
cleared. When PEN is set, the ADPCM block
will start converting. When pausing the playback
stream is desired, audio data should not be sent
to the codec causing an underrun. This can be
accomplished by disabling the DMA controller
or not sending data in PIO mode. The underrun
will be detected by the CS4231A and the adapta-
tion will freeze. As data is sent to the codec,
adaptation is resumed. It is critical that all play-
back ADPCM samples are sent to the codec,
since dropped samples will cause errors in the
adaptation. Whereas toggling PEN resets the ac-
cumulator and step size, the APAR bit (I17) only
resets the accumulator without affecting the step
size.
DMA Registers
The DMA registers allow easier integration of
the CS4231A in ISA systems. Peculiarities of the
ISA DMA controller require an external count
mechanism to notify the host CPU of a full
DMA buffer via interrupt. The programmable
DMA Base registers provide this service.
The act of writing a value to the Upper Base
register causes both Base registers to load the
Current Count register. DMA transfers are en-
abled by setting the PEN/CEN bit while
PPIO/CPIO is clear. (PPIO/CPIO can only be
changed while the MCE bit is set.) Once trans-
fers are enabled, each sample that is transferred
by a DMA cycle will decrement the appropriate
Current Count register (with the exception of the
ADPCM format) until zero is reached. The next
sample after zero generates an interrupt and re-
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