CS4231A Datasheet, PDF (14/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
Mono Output with Mute Control
The mono output, MOUT, is a sum of the left
and right output channels, attenuated by 6dB to
prevent clipping at full scale. The mono out
channel can be used to drive the PC-internal
mono speaker using an appropriate drive circuit.
This approach allows the traditional PC-sounds
to be integrated with the rest of the audio sys-
tem. Figure 5 illustrates a typical speaker driver
circuit. The mute control is independent of the
line outputs allowing the mono channel to mute
the speaker without muting the line outputs. The
power-up default has MIN and MOUT enabled
to provide a pass-through for the beeps heard at
power-up.
+5V
Ferrite Bead
470 pF
MOUT
0.1 µF
47
10 kΩ
0.22 µF
1 µF +
46
3
21 ⁷
1 µF ₊
5 ^{16 kΩ}
8
RESDRV
MC34119
0.1 µF
0.1 µF
Figure 5. Mono Output
Miscellaneous Analog Signals
The LFILT and RFILT pins must have a 1000 pF
NPO capacitor to analog ground. These capaci-
tors, along with an internal resistor, provide a
single-pole low-pass filter used at the inputs to
the ADCs. By placing these filters at the ADC
inputs, low-pass filters at each analog input pin
are avoided.
The VREFI pin is used to lower the noise of the
internal voltage reference. A 10µF and 0.1µF ca-
pacitor to analog ground should be connected
with a short wide trace to this pin. No other con-
nection should be made, since noise coupling
onto this pin can degrade the analog perform-
ance of the codec. Likewise, digital signals
should be kept away from VREFI for similar
reasons.
The VREF pin is typically 2.1 V and provides a
common mode signal for single-supply external
circuits. VREF only supports DC loads and
should be buffered if AC loading is needed. For
typical use, a 0.47 µF capacitor should be con-
nected to VREF. The signal-to-noise ratio of the
microphone inputs can be improved by increas-
ing the capacitance on VREF to 10 µF.
DIGITAL HARDWARE DESCRIPTION
The digital hardware consist of the data bus, ad-
dress bus, and control signals needed for the
parallel bus, as well as an interrupt and DMA
signals.
Parallel Data Interface
The 8-bit parallel port of the CS4231A provides
an interface which is compatible with most com-
puter peripheral busses. This parallel interface is
designed to operate on the Industry Standard Ar-
chitecture (ISA) bus, but the CS4231A will
easily interface with other buses such as EISA
and Microchannel. Two types of accesses can
occur via the parallel interface: Programmed I/O
(PIO) access, and DMA access.
There is no provision for the CS4231A to "hold
off" or extend a cycle occurring on the parallel
interface. Therefore, the internal architecture of
the CS4231A accepts asynchronous parallel bus
cycles without interfering with the flow of data
to or from the ADC and DAC sections.
FIFOs
The CS4231A contains 16-sample FIFOs in both
the playback and capture paths. The FIFOs are
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DS139PP2