CS4231A Datasheet, PDF (35/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
Pin Control (I10)
D7 D6 D5 D4 D3 D2 D1 D0
XCTL1 XCTL0 res res DEN res IEN res
IEN
Interrupt Enable: This bit enables the
interrupt pin. The Interrupt pin will re-
flect the value of the INT bit of the
Status register (R2). The interrupt
pin is active high.
0 - Interrupt disabled
1 - Interrupt enabled
DEN
Dither Enable: When set, triangular
pdf dither is added before truncating
the ADC 16-bit value to 8-bit, un-
signed data. Dither is only active in
the 8-bit unsigned mode.
0 - Dither disabled
1 - Dither enabled
XCTL1-XCTL0 XCTL Control: These bits are reflected
on the XCTL1,0 pins of the
CS4231A.
0 - TTL logic low on XCTL1,0 pins
1 - TTL logic high on XCTL1,0 pins
This registers initial state after reset is: 00xx0x0x
Error Status and Initialization (I11, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0
ORL1-ORL0
Overrange Left Detect: These bits
determine the overrange on the left
ADC channel. These bits are up-
dated on a sample by sample basis.
0 - Less than -1.5 dB from full scale
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
ORR1-ORR0 Overrange Right Detect: These bits
determine the overrange on the
Right ADC channel.
0 - Less than -1.5 dB from full scale
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
DRS
DRQ Status: This bit indicates the
current status of the PDRQ and
CDRQ pins of the CS4231A.
0 - CDRQ AND PDRQ are presently
inactive
1 - CDRQ OR PDRQ are presently
active
ACI
Auto-calibrate In-Progress: This bit
indicates the state of calibration. The
length of time high is dependent on
the calibration mode selected.
0 - Calibration not in progress
1 - Calibration is in progress
PUR
Playback underrun: This bit is set
when playback data has not arrived
from the host in time to be played.
As a result, if DACZ = 0, the last
valid sample will be sent to the
DACs. This bit is set when an error
occurs and is cleared when the
Status register (R2) is read.
COR
Capture overrun: This bit is set when
the capture data has not been read
by the host before the next sample
arrives. The old sample will not be
overwritten and the new sample will
be ignored. This bit is set when an
error condition occurs and is cleared
when the Status register (R2) is read.
The SER bit in the Status register (R2) is simply
a logical OR of the COR and PUR bits. This
enables a polling host CPU to detect an error
condition while checking other status bits.
This register’s initial state after reset is: 00000000
DS139PP2
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