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CS4231A Datasheet, PDF (34/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC
CS4231A
Interface Configuration (I9)
D7 D6 D5 D4 D3 D2 D1 D0
CPIO PPIO res CAL1 CAL0 SDC CEN PEN
PEN
CEN
SDC
Playback Enable. This bit enables
playback. The CS4231A will
generate PDRQ and respond to
PDAK signals when this bit is en-
abled and PPIO=0. If PPIO=1, PEN
enables PIO playback mode. PEN
may be set and reset without setting
the MCE bit.
0 - Playback Disabled (PDRQ and
PIO inactive)
1 - Playback Enabled
Capture Enabled. This bit enables the
capture of data. The CS4231A will
generate CDRQ and respond to
CDAK signals when CEN is enabled
and CPIO=0. If CPIO=1, CEN en-
ables PIO capture mode. CEN may
be set and reset without setting the
MCE bit.
0 - Capture disabled (CDRQ and
PIO inactive)
1 - Capture enabled
Single DMA Channel: This bit will force
BOTH capture and playback DMA re-
quests to occur on the Playback
DMA channel. The Capture DMA
CDRQ pin will be zero. This bit
forces the CS4231A to use one
DMA channel. Should both capture
and playback be enabled in this
mode, only the playback will occur.
See the DMA section for further ex-
planation.
0 - Dual DMA channel mode
1 - Single DMA channel mode
CAL1,0
Calibration: These bits determine
which type of calibration the
CS4231A performs whenever the
Mode Change Enable (MCE) bit, R0,
changes from 1 to 0. The number of
sample periods required for calibra-
tion is listed in parenthesis.
0 - No calibration (0, 40 the first time)
1 - Converter calibration (136)
2 - DAC calibration (40)
3 - Full Calibration (168)
PPIO
Playback PIO Enable: This bit deter-
mines whether the playback data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
CPIO
Capture PIO Enable: This bit deter-
mines whether the capture data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
CAUTION: This register, except bits CEN and PEN,
can only be written while in Mode Change Enable
(either MCE or PMCE). See Changing Sampling
Rate section for more details.
This register’s initial state after reset is: 00x01000
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DS139PP2