CS4231A Datasheet, PDF (37/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
Alternate Feature Enable I (I16)
D7 D6 D5 D4 D3 D2 D1 D0
OLB TE CMCE PMCE SF1 SF0 SPE DACZ
DACZ
SPE
SF1,SF0
PMCE
CMCE
TE
DAC Zero: This bit will force the out-
put of the playback channel to AC
zero when an underrun error occurs
1 - Go to center scale
0 - Hold previous valid sample
Serial Port Enable. When enabled,
audio data from the ADCs is sent
out SDOUT and audio data from
SDIN is sent to the DACs. MCE
must be set before this bit can be
changed.
1 - Enable serial port
0 - Disable serial port. Parallel port
used for audio data.
Serial Format. Selects the format of
the serial port when enabled by
SPE. MCE must be set before these
bits can be changed.
0 - 64-bit enhanced
1 - 64-bit
2 - 32-bit
3 - Reserved.
Playback Mode Change Enable. When
set, it allows modification of the ste-
reo/mono and audio data format bits
(D7-D4) for the playback channel,
I8. MCE in R0 must be used to
change the sample frequency.
Capture Mode Change Enable. When
set, it allows modification of the ste-
reo/mono and audio data format bits
(D7-D4) for the capture channel, I28.
MCE in R0 must be used to change
the sample frequency.
Timer Enable: This bit, when set, will
enable the timer to run and interrupt
the host at the specified frequency
in the timer registers.
0 - Timer Disabled - Does not count
1 - Timer Enabled - Counts down
DS139PP2
OLB
Output Level Bit: Sets the analog out-
put level. When clear, analog line
outputs are attenuated 3 dB.
0 - Full scale of 2 Vpp (-3 dB)
1 - Full scale of 2.8 Vpp (0 dB)
This register’s initial state after reset is: 00000000
Alternate Feature Enable II (I17)
D7 D6 D5 D4 D3 D2 D1 D0
TEST TEST TEST TEST res APAR XTALE HPF
HPF
High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset of 0.
0 - disabled
1 - enabled
XTALE
Crystal Enable. When set, both
crystals are always active. When
clear, only the crystal selected by
C2SL, I8, is active with the other
crystal powered down. This bit is
normally set when working with
games software that switch sample
frequencies often.
APAR
ADPCM Playback Accumulator Reset.
While set, the Playback ADPCM
accumulator is held at zero. Used
when pausing a playback stream.
TEST
Factory Test. These bits are used for
factory testing and must remain at 0
for normal operation.
This register’s initial state after reset is: 0000x000.
Left Line Input Control (I18)
D7 D6 D5 D4 D3 D2 D1 D0
LLM res res LLG4 LLG3 LLG2 LLG1 LLG0
LLG4-LLG0
Left Line, LLINE, Mix Gain. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 5.
LLM
Left Line Mute. When set to 1, the left
Line input, LLINE, to the mixer, is
muted.
This register’s initial state after reset is: 1xx01000.
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