CS4231A Datasheet, PDF (15/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
transparent and have no programming associated
with them.
When playback is enabled, the playback FIFO
continually requests data until the FIFO is full,
and then makes requests as positions inside the
FIFO are emptied, thereby keeping the playback
FIFO as full as possible. Thus when the system
cannot respond within a sample period, the FIFO
is emptied, avoiding a momentary loss of audio
data. If the FIFO runs out of data, the last valid
sample can be continuously output to the DACs
(if DACZ in I16 is set) which will eliminate
pops from occurring.
When capture is enabled, the capture FIFO tries
to continually stay empty by making requests
every sample period. Thus when the system can-
not respond within a sample period, the capture
FIFO starts filling thereby avoiding a loss of
data in the audio data stream.
High Current Data Bus Drivers
The CS4231A provides 16 mA drivers eliminat-
ing the need for off chip drivers in many cases.
If a full 24 mA drive is required, the appropriate
direction and driver select lines are provided.
The current drivers are provided for the data bus,
DMA request line, and the interrupt request line.
PIO Registers Interface
The first type of parallel bus access is pro-
grammed I/O (PIO) to the four control registers.
The control registers allow access to status,
audio data, and all indirect registers via the in-
dex registers. The RD and WR signals are used
to define the read and write cycles respectively.
The PIO register cycle is defined by the asser-
tion of the CS4231A CS signal while the DMA
acknowledge signals, CDAK and PDAK, are in-
active. For read cycles, the CS4231A will drive
data on the DATA lines while the host asserts the
RD strobe. Write cycles require the host to assert
data on the DATA lines and strobe the WR sig-
DS139PP2
nal. The CS4231A will latch data into the PIO
register on the rising edge of the WR strobe. The
CS4231A CS signal should remain active until
after completion of the read or write cycle. I/O
cycles are the only type of cycle which can ac-
cess the internal control and status registers.
When reading or writing audio data via PIO, the
Status register (R2) indicates which byte of the
audio sample is ready. The Status register does
not have to be read after every byte; however,
once all bytes of a sample are transferred, the
Status register must be read before the next sam-
ple can be transferred.
The audio data interface typically uses DMA re-
quest/grant pins to transfer the digital audio data
between the CS4231A and the bus. The
CS4231A is responsible for asserting a request
signal whenever the CS4231A’s internal buffers
need updating. The logic interfaced with the
CS4231A responds with an acknowledge signal
and strobes data to and from the CS4231A, 8
bits at a time. The CS4231A keeps the request
pin active until the appropriate number of 8-bit
cycles have occurred to transfer one audio sam-
ple. Notice that different audio data types will
require a different number of 8-bit transfers.
DMA Interface
The second type of parallel bus cycle on the
CS4231A is a DMA transfer. DMA cycles are
distinguished from PIO register cycles by the as-
sertion by the CS4231A of a CDRQ (or PDRQ)
followed by an acknowledgment by the host by
the assertion of CDAK (or PDAK). While the
acknowledgment is received from the host, the
CS4231A assumes that any cycles occurring are
DMA cycles and ignores the addresses on the
address lines and the CS line.
The CS4231A may assert the DMA request sig-
nal at any time. Once asserted, the DMA request
will remain asserted until a DMA cycle occurs to
the CS4231A. Once the falling edge of the final
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