CS4231A Datasheet, PDF (21/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
All outputs are muted (DACs and mixer)
The mixer is calibrated
The ADCs are calibrated
The DACs are calibrated
All outputs are unmuted
Changing Sampling Rate
The internal states of the CS4231A are synchro-
nized by the selected sampling frequency defined
in the Fs and Playback Data Format register (I8).
The changing of either the clock source or the
clock frequency divide requires a special se-
quence for proper CS4231A operation:
1) Place the CS4231A in Mode Change En-
able using the MCE bit of the Index
Address register (R0).
2) During a single write cycle, change the
Clock Frequency Divide Select (CFS)
and/or Clock 2 Source Select (C2SL) bits
of the Fs & Playback Data Format register
(I8) to the desired value. (The data format
may also be changed.)
3) The CS4231A resynchronizes its internal
states to the new clock. During this time
the CS4231A will be unable to respond at
its parallel interface. Writes to the
CS4231A will not be recognized and reads
will always return the value 80 hex.
4) The host now polls the CS4231A’s Index
Address register (R0) until the value
80 hex is no longer returned.
5) Once the CS4231A is no longer responding
to reads with a value of 80 hex, normal op-
eration can resume and the CS4231A can
be removed from MCE.
The CSL and CFS bits cannot be changed unless
the MCE bit has been set. Attempts to change
the Data Format registers (I8, I28) or Interface
Configuration register (I9, except CEN and
PEN) without MCE set, will not be recognized.
DS139PP2
When fast changing of sample frequency is de-
sired, the XTALE bit (I17) should be set. When
set, both crystals are kept running thereby pro-
viding the fastest switching time (80h never
appears) between sample frequencies. When
XTALE is cleared, the unused crystal is powered
down to minimize noise coupling. This causes
80h to appear after leaving an MCE cycle until
the newly selected crystal is operational. XTALE
(and the No Calibration mode, I9) provide the
fastest switching time for applications such as
games that constantly change the sample fre-
quency.
Changing Audio Data Formats
In MODE 1, MCE must be used to select the
audio data format in I8. Since MCE causes a
calibration cycle, it is not ideal for full-duplex
operation. In MODE 2, individual Mode Change
Enable bits for capture and playback are pro-
vided in register I16. MCE (R0) must still be
used to select the sample frequency, but PMCE
(for playback) and CMCE (for capture) allow
changing their respective data formats without
causing a calibration to occur. Setting PMCE
(I16) clears the playback FIFO and allows the
upper four bits of I8 to be changed. Setting
CMCE (I16) clears the capture FIFO and allows
the upper four bits of I28 to be changed.
Audio Data Formats
In MODE 1 operation, all data formats of the
CS4231A are in "little endian" format. This for-
mat defines the byte ordering of a multibyte
word as having the least significant byte occupy-
ing the lowest memory address. Likewise, the
most significant byte of a little endian word oc-
cupies the highest memory address.
The sample frequency is always selected in the
Fs and Playback Data Format register (I8). In
MODE 1 the same register, I8, determines the
audio data format for both playback and capture;
however, in MODE 2, I8 only selects the play-
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