CS4231A Datasheet, PDF (36/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
MODE and ID (I12)
D7 D6 D5 D4 D3 D2 D1 D0
1 MODE2 res res ID3 ID2 ID1 ID0
ID3-ID0
Codec ID: These four bits indicate the
ID of the codec. Revisions are con-
tained in indirect register 25. These
bits are read only.
1010
MODE2
MODE 2: Enables the expanded mode
of the CS4231A. Must be set to en-
able access to indirect registers
16-31 and their associated features.
0 - MODE 1: CS4248 "look-alike".
1 - MODE 2: Expanded features.
This register’s initial state after reset is: 10xx1010
Loopback Control (I13)
D7 D6 D5 D4 D3 D2 D1 D0
LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 res LBE
LBE
Loopback Enable: When set to 1, the
ADC data is digitally mixed with data
sent to the DACs.
0 - Loopback disabled
1 - Loopback enabled
LBA5-LBA0
Loopback Attenuation: These bits
determine the attenuation of the loop-
back from ADC to DAC. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. See Table 6.
This register’s initial state after reset is: 000000x0
Playback Upper Base (I14)
D7 D6 D5 D4 D3 D2 D1 D0
PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0
PUB7-PUB0
Playback Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. The Current
Count registers cannot be read.
When set for MODE 1 or SDC, this
register is used for both the Play-
back and Capture Base registers.
This register’s initial state after reset is: 0000000
Playback Lower Base (I15)
D7 D6 D5 D4 D3 D2 D1 D0
PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0
PLB7-PLB0
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. When set for
MODE 1 or SDC, this register is
used for both the Playback and Cap-
ture Base registers.
This register’s initial state after reset is: 00000000
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DS139PP2