CS4231A Datasheet, PDF (30/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

PU/L
SER
CRDY
CL/R
CU/L
30
CS4231A
Playback Upper/Lower Byte: This bit
indicates whether the playback data
needed is for the upper or lower
byte of the channel. In ADPCM it in-
dicates, along with PL/R, which one
of four ADPCM bytes is needed.
0 - Lower or 1/3 ADPCM byte needed
1 - Upper, any 8-bit mode, or 2/4
ADPCM byte needed
Sample Error: This bit indicates that a
sample was not serviced in time and
an error has occurred. The bit indi-
cates an overrun for capture and
underrun for playback. If both the
capture and playback are enabled,
the source which set this bit can not
be determined. However, the Alter-
nate Feature Status register (I24)
can indicate the exact source of the
error.
Capture Data Ready. The Capture
Data register (R3) contains data
ready for reading by the host. This
bit would be used for direct pro-
grammed I/O data transfers.
0 - Data is stale. Do not reread the
information.
1 - Data is fresh. Ready for next
host data read.
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Left channel or
Right channel in all audio data for-
mats except ADPCM. In ADPCM it
indicates whether the first two or last
two bytes of a 4-byte set (8 ADPCM
samples) is waiting.
0 - Right or 3/4 ADPCM byte waiting
1 - Left, Mono, or 1/2 ADPCM byte
waiting
Capture Upper/Lower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte
of the channel. In ADPCM it indi-
cates, along with CL/R, which one of
four ADPCM bytes is waiting.
0 - Lower or 1/3 ADPCM byte waiting
1 - Upper, any 8-bit mode, or 2/4
ADPCM byte waiting
Note on PRDY/CRDY: These two bits are de-
signed to be read as one when action is required
by the host. For example, when PRDY is set to
one, the device is ready for more data; or when
the CRDY is set to one, data is available to the
host. The definition of the CRDY and PRDY bits
are therefore consistent in this regard.
I/O Data Registers
The PIO Data register is two registers mapped to
the same address. Writes to this register send
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
During initialization and power down, this regis-
ter CANNOT be written and is always read
10000000 (80h)
Capture I/O Data Register (R3, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD7-CD0
Capture Data Port. This is the control
register where capture data is read
during programmed I/O data trans-
fers.
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register (R2).
Once all relevant bytes have been read, the state
machine will point to the last byte of the sample.
Once the Status register (R2) is read and a new
sample is received from the FIFO, the state ma-
chine and Status register (R2) will point to the
first byte of the new sample.
DS139PP2