CS4231A Datasheet, PDF (26/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
loads the Current Count register with the values
in the Base registers.
For all data formats except ADPCM, the DMA
Base registers must be loaded with the number
of samples, minus one, to be transferred between
"DMA Interrupts". Stereo data contains twice as
many bytes as mono data but the same number
of samples. Likewise, 16-bit data contains twice
the number of bytes as 8-bit data but the same
number of samples. The equation for loading the
DMA Base registers is:
DMA Base register₁₆ = N_S - 1
Where N_S is the number of samples transferred
between interrupts and the "DMA Base regis-
ter₁₆" consists of the concatenation of the upper
and lower DMA Base registers.
For the ADPCM data format, the contents of the
DMA Base registers are calculated differently
from any other data format. In the ADPCM for-
mat the data is transferred 4 bytes at a time.
Each four byte word transferred, decrements the
DMA Current Count register. The Base registers
must be loaded with the number of BYTES to be
transferred between "DMA interrupts", divided
by four, minus one. The same calculation is used
whether the data format is stereo or mono
ADPCM. The 4-byte word contains 8 mono
ADPCM samples or 4 stereo ADPCM samples.
The equation for loading the DMA Base regis-
ters is:
DMA Base register₁₆ = N_b/4 - 1
Where N_b is the number of BYTES transferred
between interrupts and the "DMA Base regis-
ter₁₆" consists of the concatenation of the upper
and lower DMA Base registers.
Playback DMA Registers
The playback DMA registers (I14/15) are used
for sending playback data to the DACs in
26
MODE 2. In MODE 1 or when SDC = 1, these
registers (I14/15) are used for both playback and
capture.
When the playback Current Count register rolls
under, the Playback Interrupt bit, PI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (I24). When SDC = 1, PI re-
flects the status of I14/I15 for both playback and
capture.
Capture DMA Registers
The Capture DMA Base registers (I30/31) pro-
vide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex op-
eration, capture and playback can occur
simultaneously utilizing different DMA channels.
These registers are only used in MODE 2 with
SDC = 0. If SDC in I9 is set, I14/I15 are used
for Capture DMA Base registers.
When the capture Current Count register rolls
under, the Capture Interrupt bit, CI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or by writing a "0" to the Capture
Interrupt bit, CI (I24). The CI bit is tied to the
Capture DMA base registers; therefore, when
SDC = 1, the CI bit is non-functional.
Digital Loopback
Digital Loopback is enabled via the LBE bit in
the Loopback Control register (I13). This loop-
back routes the digital data from the ADCs to
the DACs. This loopback can be digitally attenu-
ated via additional bits in the Loopback Control
register (I13). Loopback is then summed with
DAC data supplied at the digital bus interface.
When loopback is enabled, it will "freerun" syn-
chronous with the sample rate. The digital
loopback is shown in the CS4231A Block Dia-
gram on the front cover. This loopback can be
DS139PP2