CS4231A Datasheet, PDF (29/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
Index Address Register (R0)
D7 D6 D5 D4 D3 D2 D1 D0
INIT MCE TRD IA4 IA3 IA2 IA1 IA0
IA3-IA0
Index Address: These bits define the
address of the CS4231A register ac-
cessed by the Indexed Data register
(R1). These bits are read/write.
IA4
Allows access to indirect registers
16 - 31. Only available in MODE 2.
In MODE 1,this bit is reserved.
TRD
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the status
register is set. Independent for play-
back and capture interrupts.
0 - Transfers Enabled (PDRQ and
CDRQ occur uninhibited)
1 - Transfers Disabled (PDRQ and
CDRQ only occur if INT bit is 0)
MCE
Mode Change Enable: This bit must
be set whenever the sample fre-
quency,D3-D0 of I8, or the Interface
Configuration (I9) register is
changed. The exceptions are CEN
and PEN which can be changed "on-
the-fly". The DAC output is muted
when MCE is set. MCE or PMCE
(I16) may be used to changed the
playback data format, D7-D3 of I8.
MCE or CMCE (I16) may be used to
change the capture data format, D7-
D3 of I28.
INIT
CS4231A Initialization: This bit is read
as 1 when the CS4231A is in a state
in which it cannot respond to parallel
interface cycles. This bit is read-only.
Immediately after RESET (and once the CS4231A
has left the INIT state), the state of
this register is: 010x0000
During initialization and power down, this regis-
ter CANNOT be written and always reads
10000000 (80h)
Indexed Data Register (R1)
D7 D6 D5 D4 D3 D2 D1 D0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
ID7-ID0
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
During initialization and power down, this regis-
ter can NOT be written and is always read
10000000 (80h)
Status Register (R2, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CU/L CL/R CRDY SER PU/L PL/R PRDY INT
INT
PRDY
PL/R
Interrupt Status: This indicates the
status of the internal interrupt logic
of the CS4231A. This bit is cleared
by any write of any value to this reg-
ister. The IEN bit of the Pin Control
register (I10) determines whether
the state of this bit is reflected on
the IRQ pin of the CS4231A.
Read States
0 - Interrupt inactive
1 - Interrupt active
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when di-
rect programmed I/O data transfers
are desired.
0 - Data still valid. Do not overwrite.
1 - Data stale. Ready for next host
data write value.
Playback Left/Right Sample: This bit
indicates whether data needed is for
the Left channel or Right channel in
all audio data formats except
ADPCM. In ADPCM it indicates
whether the first two or last two
bytes of a 4-byte set (8 ADPCM
samples) is needed.
0 - Right or 3/4 ADPCM byte needed
1 - Left, Mono, or 1/2 ADPCM byte
needed
DS139PP2
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