CS4231A Datasheet, PDF (31/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
During initialization and power down, this regis-
ter can NOT be written and is always read
10000000 (80h)
Playback I/O Data Register (R3, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD7-PD0
Playback Data Port. This is the control
register where playback data is
written during programmed IO data
transfers.
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read and the current sam-
ple is sent to the DACs via the FIFOs.
Indirect Mapped Registers
These registers are accessed by placing the ap-
propriate index in the Index Address register
(R0) and then accessing the Indexed Data regis-
ter (R1). All reserved bits should be written zero
and may be 0 or 1 when read. Indirect registers
16-31 are only available when the MODE2 bit in
MODE and ID register (I12) is set.
Left ADC Input Control (I0)
D7 D6 D5 D4 D3 D2 D1 D0
LSS1 LSS0 LMGE res LAG3 LAG2 LAG1 LAG0
LAG3-LAG0
LMGE
Left ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 4.
Left Mic Gain Enable: This bit enables
the 20 dB gain stage of the left mic
input signal, LMIC.
LSS1-LSS0
Left ADC Input Source Select. These
bits select the input source for the
left ADC channel.
0 - Left Line: LLINE
1 - Left Auxiliary 1: LAUX1
2 - Left Microphone: LMIC
3 - Left Line Output Loopback
This register’s initial state after reset is: 000x0000
Right ADC Input Control (I1)
D7 D6 D5 D4 D3 D2 D1 D0
RSS1 RSS0 RMGE res RAG3 RAG2 RAG1RAG0
RAG3-RAG0
Right ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 4.
RMGE
Right Mic Gain Enable: This bit
enables the 20 dB gain stage of the
right mic input signal, RMIC.
RSS1-RSS0
Right ADC Input Select. These bits
select the input source for the right
ADC channel.
0 - Right Line: RLINE
1 - Right Auxiliary 1: RAUX1
2 - Right Microphone: RMIC
3 - Right Line Out Loopback
This register’s initial state after reset is: 000x0000
Left Auxiliary #1 Input Control (I2)
D7 D6 D5 D4 D3 D2 D1 D0
LX1M res res LX1G4 LX1G3 LX1G2 LX1G1 LX1G0
LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Ta-
ble 5.
LX1M
Left Auxiliary #1 Mute. When set to 1,
the left Auxiliary #1 input, LAUX1, to
the mixer, is muted.
This register’s initial state after reset is: 1xx01000.
DS139PP2
31