CS4231A Datasheet, PDF (27/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

CS4231A
used to mix the incoming microphone data with
data from the DACs. Since the CS4231A allows
selection of different data formats between cap-
ture and playback, if the capture channel is set to
mono and the playback channel set to stereo, the
mono input (mic) data will be mixed into both
channels of the output mixer.
If the sum of the loopback and bus data are
greater than full scale, CS4231A will send the
appropriate full scale value to the DACs (clip-
ping).
Timer Registers
The Timer Base registers are provided for syn-
chronization, watch dog, and other functions
where a high resolution time reference is re-
quired. This counter is 16 bits and the exact time
base, listed in the register description, is deter-
mined by the crystal selected.
When the Timer Enable bit TE, in the Alternate
Feature Enable register (I16) is clear, the timer
does not count. The Timer is set by loading the
Upper and then the Lower Base register to the
appropriate values and setting TE. When the
Timer Lower Base register (I20) is loaded, the
entire 16-bit value is loaded into an internal Cur-
rent Count register which is decremented at
approximately a 10 µsec rate. When the value of
the Current Count register reaches zero, the
Timer Interrupt bit, TI, in I24 is set, and and in-
terrupt is generated if the INT bit (R2) is set. On
the next timer clock, the value of the Timer Base
registers are automatically loaded into the inter-
nal Current Count register which begin counting
to zero again. The interrupt is cleared by any
write to the Status register (R2) or by writing a
"0" to the Timer Interrupt bit, TI, in the Alternate
Feature Status register (I24). Since the timer will
continue counting down while an interrupt is
pending, interrupts will be generated at fixed
time intervals regardless of the time required to
service the interrupt (assuming the interrupt is
serviced before the next timer interrupt is gener-
ated).
Interrupts
The INT bit of the Status register (R2) always
reflects the status of the CS4231A internal inter-
rupt state. A roll-over from any Current Count
register (DMA playback, DMA capture, or
Timer) sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status regis-
ter (R2), or by clearing the appropriate bit or bits
(PI, CI, TI) in the Alternate Feature Status regis-
ter (I24).
The Interrupt Enable (IEN) bit in the Pin Control
register (I10) determines whether the interrupt
pin responds to the interrupt event in the
CS4231A. When the IEN bit is 0, the interrupt is
masked and the IRQ pin of the CS4231A is
forced low. However, the INT bit in the Status
register (R2) always responds to the counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the CS4231A in the
appropriate amount of time. The amount of time
for such data transfers depends on the frequency
selected within the CS4231A.
Should an overrun condition occur during data
capture, the last whole sample (before the over-
run condition) will be read by the DMA
interface. A sample will not be overwritten while
the DMA interface is in the process of transfer-
ring the sample.
Should an underrun condition occur in a play-
back case, the last valid sample will be output
(assuming DACZ = 0) to the DACs which will
mask short duration error conditions. When the
next complete sample arrives from the host com-
puter the data stream will resume on the next
sample clock.
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