CS4231A Datasheet, PDF(28/76 Page) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

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CS4231A Datasheet, PDF (28/76 Pages) List of Unclassifed Manufacturers – PARALLEL INTERFACE MULTIMEDIA AUDIO CODEC

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CS4231A

CS4231A REGISTER MAPPING

Addr.

R0 0

R1 1

R2 2

R3 3

Index Address register

Indexed Data register

Status register

PIO Data register

Table 1. Direct Registers

The two address pins of the CS4231A allow ac-

cess to four 8-bit registers. Two of these registers

provide indirect access to more CS4231A regis-

ters via an index register. The other two registers

provide status information and allow audio data

to be transferred to and from the CS4231A with-

out using DMA cycles or indexing.

Physical Mapping

The PIO registers are I/O mapped via four loca-

tions. Two address pins provide access to all of

the CS4231Aâs registers. The four direct registers

are shown in Table 1. The first two direct regis-

ters are used to access 32 indirect registers

shown in Table 2. As indicated by the arrows,

the Index Address register (R0) points to the in-

direct register that is accessed through the

Indexed Data register (R1).

This section describes all the direct and indirect

registers. Table 3 details a summary of each bit

in each register with Tables 4 through 10 illus-

trating the majority of decoding needed when

programming the CS4231A and are included for

reference. Tables 4 through 8 indicate gain set-

tings at internal nodes. If OLB= 1 then the

output will reflect the gain setting. If OLB= 0,

the output will be attenuated by 3 dB as indi-

cated in the specifications. The CS4231A

powers up into the reset state which is defined as

MODE 1. MODE 1 is backwards compatible

with the CS4248 and only allows access to the

first 16 indirect registers. Setting the MODE2 bit

in the MODE and ID register (I12) enables

MODE 2 which allows access to indirect regis-

ters 16 through 31 and enables all the features of

the CS4231A.

Index

I10

I11

I12

I13

I14

I15

I16

I17

I18

I19

I20

I21

I22

I23

I24

I25

I26

I27

I28

I29

I30

I31

Left ADC Input Control

Right ADC Input Control

Left Aux #1 Input Control

Right Aux #1 Input Control

Left Aux #2 Input Control

Right Aux #2 Input Control

Left DAC Output Control

Right DAC Output Control

Fs & Playback Data Format

Interface Configuration

Pin Control

Error Status and Initialization

MODE and ID (MODE2 bit)

Loopback Control

Playback Upper Base Count

Playback Lower Base Count

Alternate Feature Enable I

Alternate Feature Enable II

Left Line Input Control

Right Line Input Control

Timer Low Base

Timer High Base

RESERVED

Alternate Feature Enable III

Alternate Feature Status

Version / Chip ID

Mono Input & Output Control

RESERVED

Capture Data Format

RESERVED

Capture Upper Base Count

Capture Lower Base Count

Table 2. Indirect Registers

DS139PP2

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