M13S64322A Datasheet, PDF (8/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
AC Timing Parameter & Specifications-continued
Parameter
ACTIVE to PRECHARGE command
AUTO REFRESH, ACTIVE command
period
Symbol
t_RAS
-4
MIN
MAX
9t_CK
120,000
-5
MIN
MAX
8t_CK
120,000
ns
t_RC
14t_CK
12t_CK
ns
RAS to CAS delay for Read
t_RCDRD
4t_CK
3t_CK
ns
RAS to CAS delay for Write
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B
command
Write recovery time
Write data in to Read command delay
Load Mode Register / Extended Mode
register cycle time
DQS read preamble
DQS read postamble
DQS valid window
Power down entry time
Power down exit time
Exit self refresh to READ command
Exit self refresh to non-READ command
Average periodic refresh interval
t_RCDWR
t_RP
2t_CK
20
2t_CK
ns
20
ns
t_RRD
3
3
t_CK
t_WR
2
t_WTR
1
2
t_CK
1
t_CK
t_LMRD
1
1
t_CK
t_RPRE
0.9
1.1
0.9
1.1
t_CK
t_RPST
0.4
0.6
0.4
0.6
t_CK
t_DQSV
0.35
0.35
t_CK
t_PDENT
t_IS+1 t_CK
t_IS+2 t_CK
t_IS+1 t_CK
t_IS+2 t_CK
ns
t_PDEX
t_IS+1 t_CK
t_IS+2 t_CK
t_IS+1 t_CK
t_IS+2 t_CK
ns
t_XSR
200
200
t_CK
t_XSA
12
12
t_CK
t_REFI
15.6
15.6
us
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
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