M13S64322A Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Revision History
Preliminary
Revision 0.5 (May 03, 2007)
- Delete BGA ball name of packing dimensions
Revision 0.4 (May 14,2002)
- Change AC Parameters
Revision
Version
tRC
tRP
-4
13 tCK
4 tCK
Rev. 0.3
-5
11 tCK
3 tCK
-4
14 tCK
20 ns
Rev. 0.4
-5
12 tCK
20 ns
Revision 0.3 (December 13,2001)
- The Max / Min value of D, D1, E, E1 (LQFP 100L PKG outline dimension) are added.
Revision 0.2 (Agu 31,2001)
- Changed DC Current
Revision
Rev. 0.1
Version
-4
-5
IDD4R
330
-
IDD5
305
260
Rev. 0.2
-4
-5
385
-
350
285
Revision
IDD6
Rev. 0.1
CKE ≦0.2
2.5mA
Rev. 0.2
CKE≦0.2, tCK =∞
CKE≦0.2, tCK = tCK (min)
2.5mA
7mA
- Added 144 Ball FBGA Pin arrangement.
- Added BGA 144B Package Outline.
Revision 0.1 (April 11,2001)
- Original
M13S64322A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
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