M13S64322A Datasheet, PDF (27/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than t_XSR for locking of DLL.
CLK
CLK
COMMAND
CKE
Sel f
Ref res h
Au t o
Ref res h
tXSA
tXSR
Read
Power down
The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of
the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce power consumption. All the banks should be in
idle state prior to entering the precharge power down mode and CKE should be set high at least 1t_CK+1t_IS prior to row active remain
command. During power down, refresh operations cannot be performed, therefore the device cannot remain in power down mode
longer than the refresh period (t_REFI) of the device.
CLK
CLK
COMMAND
CKE
Precharge
Prec harge
power
d ow n
Entry
Prec harge
power
down
E xi t
Active
Active
power
down
Entry
Active
power
down
E xi t
Read
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
27/49