M13S64322A Datasheet, PDF (10/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Basic Functionality
Preliminary
M13S64322A
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as V_TT & V_REF).
2. Start clock and maintain stable condition for a minimun of 200us.
3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. Issue EMRS to enable DLL.
*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.
*2 7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional
200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
Power up & Initialization Sequence
0
CLK
CLK
Command
precharg e
All Banks
1
2
3
4
5
tRP
MRS
precharg e
EMRS Dll Reset All Banks
6
7
8
tRP
1st Auto
Re fre sh
9
10 11 12 13
14 15 16 17 18 19
tRC
2nd Auto
Re fre sh
min. 200 Cycle
tRC
Mode
A ny
Register Set C o m m a n d
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
10/49