M13S64322A Datasheet, PDF(2/49 Page) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

M13S64322A Datasheet, PDF (2/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

◁

ESMT

DDR SDRAM

Features

Preliminary

M13S64322A

512K x 32 Bit x 4 Banks

Double Data Rate

Synchronous DRAM

z JEDEC Standard

z Internal pipelined double-data-rate architecture, two data access per clock cycle

z Bidirectional data strobe(DQS)

z On-chip DLL

z Differential clock inputs (CLK and CLK )

z DLL aligns DQ and DQS transition with CLK transition

z Quad bank operation

z CAS Latency : 2, 3, 4

z Burst Type : Sequential and Interleave

z Burst Length : 2, 4, 8

z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

z Data I/O transitions on both edges of data strobe (DQS)

z DQS is edge-aligned with data for reads; center-aligned with data for WRITE

z DM0~DM3 for write masking only

z VDD = 2.5V Â± 5%, VDDQ = 2.5V Â± 5%

z Auto & Self refresh

z 15.6us refresh interval (2K / 32ms refresh)

z 1 DQS for QFP (4 DQS for FBGA)

z SSTL-2 I/O interface

z 100pin LQFP or QFP package (optional FBGA package, 144 balls, 0.5mm ball size, 0.8mm pitch)

Operating Frequencies:

CAS

Latency

Maximum Operating Frequency

-4

-5

250MHz

200MHz

Elite Semiconductor Memory Technology Inc.

Publication Date : May. 2007

Revision : 0.5

2/49

▷