M13S64322A Datasheet, PDF (6/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
DC Specifications
Parameter
Symbol
Test Condition
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down Standby
Current
IDD0
IDD1
t_RC = t_RC (min), t_CK = t_CK (min)
Active - Precharge
Burst = 2, t_RC = t_RC (min), CL=3, I_OUT = 0mA,
Active-Read-Precharge
IDD2P CKE ≤ V_IL(max), t_CK = t_CK (min), All banks idle
Idle Standby Current
Active Power-down Standby
Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
IDD2N ^{CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK}
(min)
IDD3P All banks ACT, CKE ≤ V_IL(max), t_CK = t_CK (min)
IDD3N
IDD4R
IDD4W
IDD5
IDD6
One bank; Active-Precharge, t_RC = t_RAS(max),
t_CK = t_CK (min)
Burst=2, CL=3, t_CK = t_CK (min), I_OUT = 0mA
Burst=2, CL=3, t_CK = t_CK (min)
t_RC (min)
CKE ≤ 0.2V, t_CK = ∞
CKE ≤ 0.2V, t_CK = t_CK (min)
Note 1. Enable on-chip refresh and address counters.
Version
-4
-5
205
175
265
225
35
35
155
135
55
55
155
135
385
330
370
330
350
285
2.5
2.5
7
7
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA 1
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
Min
V_REF + 0.35
0.7
Max
V_REF - 0.35
V_DDQ+0.6
Unit
V
V
V
Note
1
Input Crossing Point Voltage, CLK and CLK inputs
V_IX(AC) 0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
V
2
Note: 1. V_ID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V_DD = 2.5V±5%, V_DDQ =2.5V±5%, T_A = 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A10, BA0~BA1, CKE, CS , RAS , CAS , WE )
Symbol
C_IN1
Min
Max
Unit
2.5
3.5
pF
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance (DQ0~DQ31)
Input capacitance (DM0~DM3)
C_IN2
C_OUT
C_IN3
2.5
3.5
pF
4.0
5.5
pF
4.0
5.5
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
6/49