M13S64322A Datasheet, PDF (37/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Write with Auto Precharge (@BL=4)
Preliminary
M13S64322A
0
1
CLK
CLK
CKE
2
3
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA0,BA1
A8/AP
ADDR
(A0~A7,A9~A10)
WE
DQS
DQ
DM
COMMAND
BAa
BAa
Ra
Ca
Ra
Qa0 Qa1 Qa2 Qa3
tWR
Auto prech arge start
Note1
tRP
WRITE
ACTIVE
Note 1.
The row active command of the precharge bank can be issued after t_RP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
37/49