M13S64322A Datasheet, PDF (20/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
CLK
CLK
COMMAND
0
NOP
1
2
1tCK
WRITE A
WRITE B
3
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
DQS
DQ's
Din A0 Din A1 Din B0 Din B1 Din B2 Din B3
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst and
tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a
Write command = CAS Latency clock cycles.
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
20/49