M13S64322A Datasheet, PDF (36/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Read with Auto Precharge (@BL=8)
0
1
CLK
CLK
CKE
CS
RAS
2
3
CAS
BA0,BA1
BAa
A8/AP
ADDR
Ca
(A0~A7,A9~A10)
WE
DQS(CL=3)
DQ(CL=3)
DM
COMMAND
READ
Preliminary
M13S64322A
4
5
6
7
8
9
10
HIGH
BAa
Ra
Ra
Au to prech arg e start
tRP
Note1
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
ACTIVE
Note 1.
The row active command of the precharge bank can be issued after t_RP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
36/49