M13S64322A Datasheet, PDF (45/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9 10
11 12 13 14 15 16
17 18 19
CLK
CLK
CKE
High level is required
CS
RAS
CAS
WE
BA0
BA1,A9,A10
A8/AP
A7
A1~A6
ADDRESS KEY
A0
High-Z
DQ
Minimum 200 Cycle
DQS
tRP
High-Z
Precharge
All Bank
MRS
Precharge
Dll Reset _{All Bank}
Power & Clock must be
stable for 200us
EMRS
DLL Enable
tRP
tRC
tRC
Minimum of 2 Refresh Cycles are required
1st Auto Refresh 2nd Auto Refresh
Any
Command
Mode Resister Set
: Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
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