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M13S64322A Datasheet, PDF (4/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM
ESMT
Pin Description
(M13S64322A)
Pin Name
A0~A10,
BA0,BA1
DQ0~DQ31
RAS
CAS
WE
VSS
VDD
DQS
DQS0~DQS3
Function
Address inputs
-Row address A0~A10
-Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power (=2.5V)
Bi-directional Data Strobe (LQFP)
Bi-directional Data Strobe (FBGA)
Preliminary
M13S64322A
Pin Name
Function
DM0~DM3 DQ Mask enable in write cycle
CLK, CLK
CKE
CS
VDDQ
VSSQ
VREF
NC
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage for SSTL-2
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
4/49