M13S64322A Datasheet, PDF (16/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after t_RCD from
the bank activation. The address inputs (A0~A7) determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 2, 3, 4>
0
1
CLK
CLK
2
3
4
COMMAND READ A
NOP
NOP
NOP
NOP
CAS Latency=2
DQS
DQ's
tRPRE
tRPST
Dout0 Dout1 Dout2 Dout3
5
NOP
6
NOP
7
NOP
8
NOP
CAS Latency=3
DQS
DQ's
Dout0 Dout1 Dout2 Dout3
CAS Latency=4
DQS
DQ's
Dout0 Dout1Dout2 Dout3
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
16/49