M13S64322A Datasheet, PDF (25/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
M13S64322A
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto-precharge command when t_RAS(min) is satisfied. If not, the start point of precharge operation will be
delayed until t_RAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (t_RP) has been satisfied
<Burst Length = 4, CAS Latency = 2, 3, 4>
CLK
0
1
CLK
2
3
4
5
6
7
8
COMMAND
Bank A
ACTIVE
DQS
CAS Latency=2
DQ's
CAS Latency=3
DQS
DQ's
NOP
Re a d A
Auto Precharge
t RAS( min. )
NOP
NOP
NOP
NOP
NOP
NOP
Dout 0 Dout 1 Dout 2 Dout 3
tRP
Bank can be reactivated at the
completion of precharge
Dout 0 Dout 1 Dout 2 Dout 3
DQS
RAS Latency=4
DQ's
Begin Auto-Precharge
Dout 0 Dout 1 Dout 2 Dout 3
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
25/49