M13S64322A Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (V_REF)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (V_IH/V_IL)
Input timing measurement reference level
Output timing reference level
Preliminary
M13S64322A
Value
0.5*V_DDQ
1.5
1.0
V_REF+0.35/V_REF-0.35
V_REF
V_TT
Unit
V
V
V/ns
V
V
V
AC Timing Parameter & Specifications
(V_DD = 2.5V±5%, V_DDQ=2.5V±5%, T_A =0 °C to 70 °C )(Note)
Parameter
Clock Period (CL3)
(CL4)
Symbol
t_CK
-4
MIN
MAX
4
10
-
-
-5
MIN
MAX
5
10
ns
-
-
ns
Access time from CLK/ CLK
t_AC
-0.5
0.5
-0.75
0.75
ns
CLK high-level width
t_CH
0.45
0.55
0.45
0.55
t_CK
CLK low-level width
t_CL
0.45
0.55
0.45
0.55
t_CK
Data strobe edge to clock edge
t_DQSCK
-0.5
0.5
-0.75
0.75
ns
Clock to first rising edge of DQS delay
t_DQSS
0.75
1.25
0.75
1.25
t_CK
Data-in setup time (to DQS)
t_DS
0.4
0.4
ns
Data-in hold time (to DQS)
t_DH
0.4
0.4
ns
DM setup time (to DQS)
t_DQMS
0.4
0.4
ns
DM hold time (to DQS)
t_DQMH
0.4
0.4
ns
Input setup time
t_IS
0.75
1.1
ns
Input hold time
t_IH
0.75
1.1
ns
DQS input high pulse width
t_DQSH
0.4
0.6
0.4
0.6
t_CK
DQS input low pulse width
t_DQSL
0.4
0.6
0.4
0.6
t_CK
Clock to DQS write preamble setup time
t_WPRES
0
0.5
0
0.5
t_CK
Clock to DQS write preamble hold time
t_WPREH
0.25
1.25
0.25
1.25
t_CK
Write postamble
t_WPST
0.25
0.25
t_CK
Data strobe edge to output data edge
Half Clock Period
DQ-DQS output hold time
t_DQSQ
-0.35
0.35
-0.5
0.5
ns
t_HP
t_CLmin or
t_CHmin
t_CLmin or
t_CHmin
ns
t_QH
t_HP-0.35
t_HP-0.5
ns
Data-out high-impedance windows from
CLK/ CLK
t_HZ
-0.5
0.5
-0.75
0.75
ns
Data-out low-impedance windows from
CLK/ CLK
t_LZ
-0.5
0.5
-0.75
0.75
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
7/49