M13S64322A Datasheet, PDF (33/49 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM

ESMT
Preliminary
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
M13S64322A
0
1
CLK
CLK
CKE
CS
RAS
tCH tCL
tCK
2
3
4
5
6
7
8
9
10
HIGH
tHP
Note1
tIS
tIH
CAS
BA0,BA1
BAa
BAb
A8/AP
BAa
Cb
WE
DQS
DQ
DM
tDQSCK
tRPRE
tLZ
tDQSCK
tRPST
Hi-Z
tDQSQ
Da0 Da1
Da2
tAC
Da3
tHZ
Hi-Z
tQH
tDQSS
tWPREH
tDQSL
t W P R E S^{t D Q S H}
tDS tDH tDS tDH
Db0 Db1 Db2
tWPST
Db3
Hi-Z
Hi-Z
COMMAND
READ
WRITE
Note1
tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
33/49