M14D5121632A_1 Datasheet, PDF (7/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Parameter
Symbol
Test Condition
Version
Unit
-3
t_CK = t_CK (IDD);
Refresh command every t_RFC (IDD) interval;
Auto Refresh Current IDD5 CKE is HIGH, CS is HIGH between valid commands;
mA
Other control and address bus inputs are SWITCHING;
100
Data bus inputs are SWITCHING
Self Refresh Mode;
Self Refresh Current IDD6 ^{CLK and CLK at 0V; CKE ≤ 0.2V;}
6
mA
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
All bank interleaving Reads, I_OUT = 0mA;
BL = 4, CL= CL (IDD), AL = t_RCD (IDD) – 1 × t_CK (IDD);
Operating Current
(Bank interleaving)
IDD7
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
t_RRD = t_RRD (IDD), t_RCD = 1 × t_CK (IDD);
CKE is HIGH, CS is HIGH between valid commands;
230
mA
Address bus inputs are STABLE during Deslects;
Data pattern is the same as IDD4W;
Note:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and /DQS, IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD:
LOW is defined as V_IN ≤ V_IL (AC) (max.).
HIGH is defined as V_IN V_IH (AC) (min.).
STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at V_REF = V_DDQ/2
SWITCHING is defined as:
Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks), and
DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per
clock).
6. When T_C ≧ +85 ℃, IDD6 must be derated by 80%.
IDD6 will increase by this amount if T_C ≧ +85 ℃ and double refresh option is still enabled.
7. AC Timing for IDD test conditions
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
-3
DDR2-667
Unit
(5-5-5)
CL (IDD)
tRCD (IDD)
5
t_CK
15
ns
tRC (IDD)
60
ns
tRRD (IDD)
10
ns
tCK (IDD)
3
ns
tRAS (IDD) min.
45
ns
tRAS (IDD) max.
70000
ns
tRP (IDD)
15
ns
tRFC (IDD)
105
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
7/59