M14D5121632A_1 Datasheet, PDF (52/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Operation Temperature Condition (TC) -40°C~95°C
Asynchronous CKE Low event
DDR2 SDRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “LOW” during any valid operation, the device is not guaranteed to preserve the contents of array. If this event occurs,
memory controller must satisfy t_DELAY before turning off the clocks. Stable clocks must exist at the input of device before CKE is
raised “HIGH” again. The device must be fully re-initialized (steps 4 ~ 13) as described in initialization sequence. The device is
ready for normal operation after the initialization sequence.
CLK
CLK
CKE
tCK
tDELAY
Stable clocks
CKE asynchronously
drops low
Clocks can be turned off
after this point
Clock Frequency change in Precharge Power-Down mode
DDR2 SDRAM input clock frequency can be changed under following condition:
The device is in Precharge Power-Down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2
clocks must be waited after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to
change only between t_CK (min) and t_CK (max). During input clock frequency change, ODT and CKE must be held at stable LOW
levels. Once input clock frequency is changed, stable new clocks must be provided before Precharge Power-Down may be exited
and DLL must be RESET via MRS after Precharge Power-Down exit. Depending on new clock frequency an additional MRS
command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After the
DLL lock time, the device is ready to operate with new clock frequency.
T0 T1 T2 T4 Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4
Tz
CLK
CLK
command
CKE
NOP NOP
NOP NOP
DLL
Reset
NOP
Vaild
ODT
tRP
tAOFD
Frequency change
occurs here
txP
Minimum 2 clocks required
before changing frequency
Stable new clock
before power down exit
200 clocks
ODT is off
during DLL RESET
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
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